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Compiler Analysis and Supports for Leakage Power Reduction on Microprocessors [chapter]

Yi-Ping You, Chingren Lee, Jenq Kuen Lee
2005 Lecture Notes in Computer Science  
This raises interests on the issues to employ architecture and compiler efforts to reduce leakage power (also known as static power) on microprocessors.  ...  We also give the equation for the compiler to decide if the employment of the power gating instructions on given program blocks will benefit the total energy reductions.  ...  We present a data-flow analysis framework [2] for a compiler to analyze the inactive states of components on a microprocessor.  ... 
doi:10.1007/11596110_4 fatcat:systm6e4hbdj3nieaxb6vdk2iq

Compilers for leakage power reduction

Yi-Ping You, Chingren Lee, Jenq Kuen Lee
2006 ACM Transactions on Design Automation of Electronic Systems  
Our compiler provides an analysis framework for utilizing instructions to reduce the leakage power.  ...  This has lead to interest in using architecture and compiler optimization to reduce leakage power (also known as static power) in microprocessors.  ...  CONCLUSIONS In the study described in this article, we investigated compiler analysis techniques aimed at reducing microprocessor leakage power.  ... 
doi:10.1145/1124713.1124723 fatcat:rvnrsiicczgsnltssb5r2acqq4

Cache exploitation in embedded systems

Jingling Xue
2005 Journal of Embedded Computing  
Unlike caches, however, scratchpads require explicit support from the compiler.  ...  To exploit the benefits of these two approaches, some high-end embedded microprocessors such as ARM10E and ColdFire MCF5 include both on-chip caches and a scratchpad.  ...  In "Exploiting Loop Behavior for Data Cache Leakage Reduction," Zhang introduces a compiler-directed approach to reducing the data cache leakage energy for loop-oriented programs.  ... 
dblp:journals/jec/Xue05 fatcat:7dhagpq3r5doxjqcx6ly3q6ppu

Compiler-directed leakage reduction in embedded microprocessors

Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori
2009 2009 IEEE International Conference on Computer Design  
For experimentation, GCC is used as the compiler infrastructure and Simplescalar-ARM is used as the detailed architectural simulator for reporting power and performance metrics for embedded applications  ...  In this paper, we investigate and report how the leakage savings in both integer and floating point units can be improved using machine-dependent and independent optimizations in a compiler-directed power  ...  Power gating is considered to be one of the most useful techniques for leakage reduction because, at the cost of low energy and performance overheads, the savings in leakage achieved by power gating can  ... 
doi:10.1109/iccd.2009.5413178 dblp:conf/iccd/RoyRK09 fatcat:tig65ieezrdjlk5yv5wy4hv5n4

Recent thermal management techniques for microprocessors

Joonho Kong, Sung Woo Chung, Kevin Skadron
2012 ACM Computing Surveys  
We summarize recent thermal management techniques for microprocessors, focusing on those that affect or rely on the microarchitecture.  ...  Floorplanning covers a range of thermal-aware floorplanning techniques for 2D and 3D microprocessors.  ...  ACKNOWLEDGMENTS This survey work was supported in part by a grant from the US NSF under grant number CRI-0551630, a grant from Intel Research, and the Korea Science and Engineering Foundation (KOSEF) grant  ... 
doi:10.1145/2187671.2187675 fatcat:bsvvqax2rbftxivi555mzzc7uy

PowerFITS: Reduce Dynamic and Static I-Cache Power Using Application Specific Instruction Set Synthesis

A.C. Cheng, G.S. Tyson, T.N. Mudge
2005 IEEE International Symposium on Performance Analysis of Systems and Software, 2005. ISPASS 2005.  
For 21 benchmarks from the MiBench suite [3], our simulation results indicate on average: a 49.4% saving for switching power; a 43.9% saving for internal power; a 14.9% saving for leakage power; a 46.6%  ...  Power consumption, performance, area, and cost are critical concerns in designing microprocessors for embedded systems such as portable handheld computing and personal telecommunication devices.  ...  Next, we present the power reduction that FITS is able to achieve in each of the component powers: switching, internal, leakage, and peak powers.  ... 
doi:10.1109/ispass.2005.1430557 dblp:conf/ispass/ChengTM05 fatcat:ty7f2esrzjfj5olhr757xzj2im

Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units

Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano
2011 IPSJ Transactions on System LSI Design Methodology  
Comprehensive real-chip evaluations have been performed to verify the leakage reduction efficiency.  ...  To reduce the leakage power consumption, functional units, such as multiplier and divider can be power-gated individually according to the workload of the execution program.  ...  The authors thank to VLSI Design and Education Center (VDEC) and Japan Science and Technology Agency (JST) CREST for their support.  ... 
doi:10.2197/ipsjtsldm.4.182 fatcat:otquktpinzga3erietntkbime4

Instruction level and operating system profiling for energy exposed software

A. Sinha, N. Ickes, A.P. Chandrakasan
2003 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The technique is shown to have an estimation error of less than 3% with trivial runtime overhead, based on a set of application programs evaluated on the StrongARM SA-1100 and Hitachi SH-4 microprocessors  ...  A technique to isolate the switching and leakage energy components of software is outlined. The energy overhead of a real-time operating system is also profiled.  ...  Min for his help with the DVS circuit and T. Furrer for the initial work of porting the eCOS operating system to StrongARM.  ... 
doi:10.1109/tvlsi.2003.819569 fatcat:ohpnaazluzb4naxm6hd6oyt2xm

Microprocessors in the Era of Terascale Integration

Shekhar Borkar, Norman P. Jouppi, Per Stenstrom
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
Power, variability, reliability, aging, and testing will pose as barriers and challenges to harness this integration capacity.  ...  Advances in microarchitecture and programming systems discussed in this paper are potential solutions.  ...  For example, load balancing remains a problem. It is conceivable to support efficient task management structures on-chip that off-load programmers/compilers for elaborate load-balancing tradeoffs.  ... 
doi:10.1109/date.2007.364597 dblp:conf/date/BorkarJS07 fatcat:bmd4yi4hz5d3dkcelij5rtbhfu

Designing high performance CMOS microprocessors using full custom techniques

William J. Grundmann, Dan Dobberpuhl, Randy L. Allmon, Nicholas L. Rethman
1997 Proceedings of the 34th annual conference on Design automation conference - DAC '97  
In this paper, we describe a full custom CMOS design methodology and supporting CAD technologies used to develop ALPHA and StrongARM microprocessors at Digital Semiconductor.  ...  Additional sections focus on two particular areas of interest: high performance low-power and full custom design benefits and verification issues. Design Automation Conference ®  ...  Acknowledgement The authors thank Bill Bowhill for his help with this paper.  ... 
doi:10.1145/266021.266353 dblp:conf/dac/GrundmannDAR97 fatcat:rzvtf3fm5zfznmbrhzw6znjj7m

TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors

Na Gong, Jinhui Wang, Shixiong Jiang, Ramalingam Sridhar
2015 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Modern microprocessors employ register files (RFs) for performance enhancement and achieving instruction level parallelism simultaneously.  ...  Simulation results on SPEC 2000 benchmarks demonstrate that TM-RF achieves up to 81.4% power savings and 17% reliability improvement on average, with minimal impact on performance.  ...  Alternatively, the second set of approaches release registers with compiler support.  ... 
doi:10.1109/tvlsi.2014.2334136 fatcat:odbpvvtipjegheztiiewhx74ay

High-quality ISA synthesis for low-power cache designs in embedded microprocessors

A. C. Cheng, G. S. Tyson
2006 IBM Journal of Research and Development  
Energy efficiency, performance, area, and cost are critical concerns in designing microprocessors for embedded systems, such as portable handheld computing and personal telecommunication devices.  ...  Experimental results show that our synthesized instruction set results in significant power reduction in the L1 instruction cache compared with ARMt instructions.  ...  Next, we present the power reduction that FITS is able to achieve in each of the switching, internal, leakage, and peak powers.  ... 
doi:10.1147/rd.502.0299 fatcat:tgvzkjoiovhlrd4lem6gfvyvpu

A proposal to introduce power and energy notions in computer architecture laboratories

Alicia Asín Pérez, Darío Suárez Gracia, Victor Viñals Yúfera
2007 Proceedings of the 2007 workshop on Computer architecture education - WCAE '07  
Power has emerged as a major concern in the microprocessor industry.  ...  For example, our experiments show that students can deduce the dynamic and static power dissipation of the Intel Pentium 4. Information that is not documented in the processor's datasheet.  ...  Acknowledgements We gratefully acknowledge Patrick Akl, Andreas Moshovos, and Jason Zebchuk for their helpful suggestions and comments on a prior version of this paper.  ... 
doi:10.1145/1275633.1275644 fatcat:fc3rsfo4yrbydmhcgzkp6gkhya

Power-Aware Compilation for Register File Energy Reduction

José L. Ayala, Alexander Veidenbaum, Marisa López-Vallejo
2003 International journal of parallel programming  
KEY WORDS: Register file management; compiler support; energy aware. 452 Ayala, Veidenbaum, and López-Vallejo  ...  Most power reduction techniques have focused on gating the clock to unused functional units to minimize static power consumption, while system level optimizations have been used to deal with dynamic power  ...  In this paper, we propose a mechanism for power-aware register file reconfiguration based on compiler support and code profiling.  ... 
doi:10.1023/b:ijpp.0000004510.66751.2e fatcat:nmhxoqj4hvgqjdret5hdihdlde

Energy-Efficient Hardware Data Prefetching

Yao Guo, Pritish Narayanan, Mahmoud Abdullah Bennaser, Saurabh Chheda, Csaba Andras Moritz
2011 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
These include compiler-assisted and hardware-based energy-aware techniques and a new power-aware prefetch engine that can reduce hardware prefetching related energy consumption by 7-11 .  ...  Combined with the effect of leakage energy reduction due to performance improvement, the total energy consumption for the memory system after the application of these techniques can be up to 12% less than  ...  We estimate the leakage and dynamic power for these caches based on the following assumptions: • Leakage Power: Leakage power increases linearly with cache size, e.g., 128 kB DL1 and IL1 caches consume  ... 
doi:10.1109/tvlsi.2009.2032916 fatcat:kt2f2lmks5df3by3drdqestgwa
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