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Towards Dynamic and Partial Reconfigurable Hardware Architectures for Cryptographic Algorithms on Embedded Devices

Arkan Alkamil, Darshika G. Perera
2020 IEEE Access  
In this case, the reconfiguration can be done on-the-fly (i.e., dynamically), without interrupting the system's operation and without human intervention.  ...  As depicted in Figure 12 , in our designs, the full and partial VOLUME XX, 2017 9 bitstreams are stored in the compact flash (CF) non-volatile memory.  ... 
doi:10.1109/access.2020.3043750 fatcat:loyavgqwzrffflknefneimyrzi

A Survey of Recent Results in FPGA Security and Intellectual Property Protection [chapter]

François Durvaux, Stéphanie Kerckhof, Francesco Regazzoni, François-Xavier Standaert
2013 Secure Smart Embedded Devices, Platforms and Applications  
Finally, we emphasize recent trends for improving IP security in FPGAs, including bitstream security, the use of code watermarking techniques and the exploitation of Physically Unclonable Functions (PUFs  ...  First, can we use FPGAs as security devices for e.g. securely and efficiently encrypting sensitive data (in particular when compared to software solutions)?  ...  IP security Since FPGAs are volatile and generic platforms, a large number of designs can be implemented on them, ranging from essentially hardware to on chip combinations of hardware and software.  ... 
doi:10.1007/978-1-4614-7915-4_9 fatcat:bp2upohaffe4nl5qlx3gykrncm

A reconfigurable Crypto Sub System for the Software Communication Architecture

Michael Grand, Lilian Bossuet, Bertrand Le Gal, Dominique Dallet, Guy Gogniat
2009 MILCOM 2009 - 2009 IEEE Military Communications Conference  
In this paper, we describe the first non-confidential reconfigurable cryptoprocessor architecture for SSCA. We provide some area estimation of processor main parts on Xilinx Virtex 4 FPGA.  ...  The Secure Software Communication Architecture (SSCA) is a standardized solution to secure SDR. This architecture needs a cryptographic processor for security purposes.  ...  DRCA configuration is set on-the-fly by the ContB through the Internal Reconfiguration Access Port (ICAP) [10] embedded in Xilinx FPGA.  ... 
doi:10.1109/milcom.2009.5379915 fatcat:pvkuleuzqjeppmxftg7g7mddzi

LifeLine for FPGA Protection: Obfuscated Cryptography for Real-World Security

Florian Stolz, Nils Albartus, Julian Speith, Simon Klix, Clemens Nasenberg, Aiden Gula, Marc Fyrbiak, Christof Paar, Tim Güneysu, Russell Tessier
2021 Transactions on Cryptographic Hardware and Embedded Systems  
We then describe the design and implementation of novel hardware obfuscation primitives based on the intrinsic structure of FPGAs.  ...  Based on our primitives, we design and implement LifeLine, a hardware design protection mechanism for FPGAs using hardware/software co-obfuscated cryptography.  ...  Our reconfiguration controller realizes both the dynamic partial reconfiguration as well as the dynamic bitstream readback for the hardware self-integrity check as detailed in Section 5.1 and Section 5.4  ... 
doi:10.46586/tches.v2021.i4.412-446 fatcat:tvapiwiqojhq7hbecgzgk7at5y

Efficient and side-channel resistant authenticated encryption of FPGA bitstreams

Andrey Bogdanov, Amir Moradi, Tolga Yalcin
2012 2012 International Conference on Reconfigurable Computing and FPGAs  
Adequate protection of the FPGA bitstream is of paramount importance to sustain the central functionality of dynamic reconfiguration in a hostile environment.  ...  State-of-the-art solutions for FPGA bitstream protection rely on encryption and authentication of the bitstream to both ensure its confidentiality, thwarting unauthorized copying and reverse engineering  ...  Furthermore, FPGA numbers will be useful in determining the necessary resources required for evaluation of security and side-channel attack resistance on FPGA-based platforms.  ... 
doi:10.1109/reconfig.2012.6416743 dblp:conf/reconfig/BogdanovMY12 fatcat:7mxdt4vrbvhidlzeqbk43hkmta

Performance of partial reconfiguration in FPGA systems

Kyprianos Papadimitriou, Apostolos Dollas, Scott Hauck
2011 ACM Transactions on Reconfigurable Technology and Systems  
Fine-grain reconfigurable devices suffer from the time needed to load the configuration bitstream. Even for small bitstreams in partially reconfigurable FPGAs this time cannot be neglected.  ...  Then, we study an FPGA-based system architecture and with real experiments we produce a cost model of Partial Reconfiguration (PR).  ...  ACKNOWLEDGMENT The authors wish to thank Dr. Christoforos Kachris for his valuable feedback that helped improving the initial manuscript.  ... 
doi:10.1145/2068716.2068722 fatcat:sp2yn7f3wbe43fwswvkaoo743q

Real-time embedded systems powered by FPGA dynamic partial self-reconfiguration: a case study oriented to biometric recognition applications

Francisco Fons, Mariano Fons, Enrique Cantó, Mariano López
2011 Journal of Real-Time Image Processing  
of the FPGA.  ...  The implementation benchmark of the AFAS either as a pure software approach on a PC platform under a dual-core processor (Intel Core 2 Duo T5600 at 1.83 GHz) or as a reconfigurable FPGA co-design (identical  ...  resources which are reconfigured on the fly to perform new functionality each time.  ... 
doi:10.1007/s11554-010-0186-1 fatcat:j5by7g5vpbfv3egkmqd6mzwhnq

Dynamic partial reconfigurable hardware architecture for principal component analysis on mobile and embedded devices

S. Navid Shahrouzi, Darshika G. Perera
2017 EURASIP Journal on Embedded Systems  
Our previous analysis illustrated that FPGA-based dynamic reconfigurable systems are currently the best avenue to overcome these challenges.  ...  Furthermore, our partial and dynamic reconfigurable hardware design achieved 79 times speedup compared to its software counterpart, and 71% space saving compared to its static reconfigurable hardware design  ...  She serves on organizing and program committees for several IEEE/ACM conferences and workshops and as a reviewer for several IEEE, Springer, and Elsevier journals.  ... 
doi:10.1186/s13639-017-0074-x fatcat:kirfxlb6hngr3ajolbvx2b7koy

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

Prateek Shantharama, Akhilesh S. Thyagaturu, Martin Reisslein
2020 IEEE Access  
One effort in this direction are the FPGA designs to support dynamic run-time reconfiguration through binary files which are commonly referred to as partial reconfiguration [206] for runtime reconfiguration  ...  [252] have proposed an SD-NoC architecture that enables on-the-fly reconfiguration of the interconnect fabric.  ... 
doi:10.1109/access.2020.3008250 fatcat:kv4znpypqbatfk2m3lpzvzb2nu

The Promise of Reconfigurable Computing for Hyperspectral Imaging Onboard Systems: A Review and Trends

Sebastian Lopez, Tanya Vladimirova, Carlos Gonzalez, Javier Resano, Daniel Mozos, Antonio Plaza
2013 Proceedings of the IEEE  
Fast processing solutions for compression and/or interpretation of hyperspectral data onboard spacecraft imaging platforms are discussed in this paper with the purpose of giving a more efficient exploitation  ...  With the advent of new hyperspectral remote sensing missions and their increased temporal resolutions, the availability and dimensionality of hyperspectral data is contin-  ...  comments and suggestions for improvement.  ... 
doi:10.1109/jproc.2012.2231391 fatcat:aepzokz6wne2dbxtlx3ij5sqau

R3TOS-Based Integrated Modular Space Avionics for On-Board Real-Time Data Processing

Adewale Adetomi, Godwin Enemali, Xabier Iturbe, Tughrul Arslan, Didier Keymeulen
2018 2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)  
It is possible to switch from one network to another on the fly, or even route new nets completely to a reconfigurable module.  ...  Figure 2.1: Dynamic Partial Reconfiguration in FPGAs frame.  ... 
doi:10.1109/ahs.2018.8541369 dblp:conf/ahs/AdetomiEIAK18 fatcat:kr7xdsvbaveqxplr6iwpdpx4me

Nature of and lessons learned from Lunar Ice Cube and the first deep space CubeSat 'Cluster'

Pamela E. Clark, Robert MacDowall, Benjamin Malphrus, Cliff Brambora, Dave Folta, William Farrell, Allen W. Lunsford, Matthew D. Grubb, Terry Hurford, Charles D. Norton, Thomas S. Pagano
2018 CubeSats and NanoSats for Remote Sensing II  
ice at the lunar poles, utilizing an active source (laser), and looking for absorption features in the returning signal; and LunaH-Map to characterize ice at or below the surface at the poles with a compact  ...  of dual communication system at Mars, and the 13 diverse cubesats being deployed from the SLS EM1 mission within the next two years.  ...  ACKNOWLEDGMENTS This work was carried out at the Jet Propulsion Laboratory, California Institute of Technology, under contract with the National Aeronautics and Space Administration.  ... 
doi:10.1117/12.2320055 fatcat:tr4juubtjvelbdn5poncqwwh2y

FPGAs in Industrial Control Applications

E Monmasson, L Idkhajine, M N Cirstea, I Bahri, A Tisan, M W Naouar
2011 IEEE Transactions on Industrial Informatics  
The aim of this paper is to review the state of the art of Field Programmable Gate Array (FPGA) technologies and their contribution in industrial control applications.  ...  To illustrate the benefit of using FPGAs in the case of complex control applications, a sensorless motor controller has been treated. This controller is based on the Extended Kalman Filter.  ...  Finally, we shall finish this enumeration by reminding that SRAM-based FPGA architecture can be reconfigured on the fly.  ... 
doi:10.1109/tii.2011.2123908 fatcat:mkjify6zlzgnjglgpyoixh53ra

From Connectivity to Advanced Internet Services: A Comprehensive Review of Small Satellites Communications and Networks

Scott C. Burleigh, Tomaso De Cola, Simone Morosi, Sara Jayousi, Ernestina Cianca, Christian Fuchs
2019 Wireless Communications and Mobile Computing  
An overview of recent advances and development trends in the field of small satellites is provided, with a special focus on telecommunication aspects such as the use of higher frequency bands, optical  ...  Recently, the availability of innovative and affordable COTS (Commercial Off-The-Shelf) technological solutions and the ever-improving results of microelectronics and microsystems technologies have enabled  ...  All other bundles are queued for transmission to the next hot spot the courier will fly over.  ... 
doi:10.1155/2019/6243505 fatcat:aaip37vahfavxexcm7xyg7lnpu

The Ultimate DataFlow for Ultimate SuperComputers-on-a-Chip, for Scientific Computing, Geo Physics, Complex Mathematics, and Information Processing [article]

Veljko Milutinovic, Erfan Sadeqi Azer, Kristy Yoshimoto, Gerhard Klimeck, Miljan Djordjevic, Milos Kotlar, Miroslav Bojovic, Bozidar Miladinovic, Nenad Korolija, Stevan Stankovic, Nenad Filipović, Zoran Babovic (+8 others)
2021 arXiv   pre-print
array accelerator for the most frequently used Machine Learning algorithms needed in bandwidth-bound applications and a flexible-structure reprogrammable accelerator for less frequently used Machine Learning  ...  This article starts from the assumption that near future 100BTransistor SuperComputers-on-a-Chip will include N big multi-core processors, 1000N small many-core processors, a TPU-like fixed-structure systolic  ...  Acknowledgements: The authors are thankful to Lars Zetterberg of KTH, Henry Markram of EPFL, Roberto Giorgi of the University of Siena, and Anton Kos of the University of Ljubljana, for their eyes opening  ... 
arXiv:2009.10593v6 fatcat:mlwkr2lclng7jexs4e62wgs5se
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