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Fuzzy Logic Partition-Based Call Admission Control for Mobile WiMAX
2011
ISRN Communications and Networking
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In this paper, we propose a fuzzy logic partition-based call admission control (FZ CAC). ...
The fuzzy logic admission control scheme was implemented in the HO portion to intelligently keep dropping probability as low as possible based on the available bandwidth. ...
In this paper, we present efficient call admission control (CAC) which is partitioned based on fuzzy logic control of the handover (HO) partition. ...
doi:10.5402/2011/171760
fatcat:2qvm6cyrjzgqhi472i3isswdwy
Load-Balancing Enhancement by a Mobile Data Collector in Wireless Sensor Networks
2020
International Journal on Smart Sensing and Intelligent Systems
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The mobile data collector can directly communicate with the base station. Indeed, the mobile data collector acts as an interface between sensor nodes and the base station. ...
LBE method divides WSN to four logical partitions. ...
Fig. 6 , shows the number of nodes death in each logical partition. Based on this figure, the logical partition 2 has the more nodes death of other logical partitions. ...
doi:10.21307/ijssis-2019-134
fatcat:7bv7fyq6bnhr7cfle2v3b3dgt4
Incremental compilation for parallel logic verification systems
2002
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Important aspects of this work include the formulation and analysis of two incremental design mapping steps: the partitioning of newly added design logic onto multiple logic processors and the communication ...
To validate our incremental compilation techniques, the developed mapping heuristics have been integrated into the compilation flow for a field-programmable gate-array-based Ikos VirtuaLogic emulator [ ...
Hard I/O indicates the average number of logic signals communicated for each partition. ...
doi:10.1109/tvlsi.2002.801614
fatcat:r6l3cna55zbsvc2jcnrj7bhiju
Temporal logic replication for dynamically reconfigurable FPGA partitioning
2002
Proceedings of the 2002 international symposium on Physical design - ISPD '02
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In this paper, we propose the idea of temporal logic replication in dynamically reconfigurable field-programmable gate array partitioning to reduce the communication cost. ...
We show that this is a very effective means to reduce the communication cost by taking advantage of the slack logic capacity available. ...
In this paper, we address the temporal partitioning problem for DRFPGA with temporal logic replication for communication cost reduction. ...
doi:10.1145/505433.505434
fatcat:bc7rk7hkdjcq7bogzb4h6d4qka
Temporal logic replication for dynamically reconfigurable fpga partitioning
2003
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we propose the idea of temporal logic replication in dynamically reconfigurable field-programmable gate array partitioning to reduce the communication cost. ...
We show that this is a very effective means to reduce the communication cost by taking advantage of the slack logic capacity available. ...
In this paper, we address the temporal partitioning problem for DRFPGA with temporal logic replication for communication cost reduction. ...
doi:10.1109/tcad.2003.814237
fatcat:4h2nkbmjpbcj7euk7tskrbpvhu
Fuzzy Based Security Threshold Determining For The Statistical En-Route Filtering In Sensor Networks
2008
Zenodo
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In this paper, we propose a fuzzy logic for determining a security threshold value in the SEF based sensor networks. ...
The fuzzy logic determines a security threshold by considering the number of partitions in a global key pool, the number of compromised partitions, and the energy level of nodes. ...
These sensor nodes have the ability to communicate either among each other or directly to the base station [4] . ...
doi:10.5281/zenodo.1060784
fatcat:tjajlkshgvckpef2vxalfumqha
Logic synthesis for field-programmable gate arrays
1994
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present a communication complexity-based decomposition technique that appears to be more suitable for FPGA synthesis than other multilevel logic synthesis methods. ...
The key is that our logic optimization technique based on reducing communication complexity is good enough to allow a simple technology mapping to work well for FPGA devices. ...
COMMUNICATION COMPLEXITY-BASED LOGIC SYNTHESIS In this section, we will give an overview of communication complexity-based logic synthesis. A detailed description can be found in [ 111. ...
doi:10.1109/43.317471
fatcat:bqpd3ulpnrdphmjvvmcm7uzxz4
Implementation of FPGA-Based Controller in Automatic Control System Platform for Launch Site
2020
Procedia Computer Science
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The schemes include the board layout and design of the logic daughter card for the architecture of the FPGA-based controller. ...
The schemes include the board layout and design of the logic daughter card for the architecture of the FPGA-based controller. ...
The fixed function FPGA programmable logic partition is called a base programmable logic module (BPLM). ...
doi:10.1016/j.procs.2020.02.007
fatcat:o3flf4vcxrgcndsb7la4e5hiym
Improving the Efficiency of Reasoning Through Structure-Based Reformulation
[chapter]
2000
Lecture Notes in Computer Science
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We investigate the possibility of improving the efficiency of reasoning through structure-based partitioning of logical theories, combined with partitionbased logical reasoning strategies. ...
To this end, we provide algorithms for reasoning with partitions of axioms in first-order and propositional logic. ...
A critical aspect of partition-based logical reasoning is the selection of a good partitioning of the theory. ...
doi:10.1007/3-540-44914-0_15
fatcat:yrkehlmyvvbedc6ncha22gt6w4
Automated Design Flow for Multi-Context FPGAs
2006
The ... Midwest Symposium on Circuits and Systems conference proceedings
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Their very fast reconfiguration time permits mapping virtual circuits efficiently, that is, a time-multiplexed execution of circuit partitions that behaves as the circuit statically implemented on a larger ...
Gate-level Temporal Partitioning The partitioning method is designed to be applicable on two-contexts FPGAs, where the logic elements are based on the usual FPGA architecture (based on logic blocks with ...
The logic element is based on a 4input LUT, and a FF that can be used for storing the LUT value or as a communication buffer. The DRLE [10] offers a 4.6ns reconfiguration time and 8 contexts. ...
doi:10.1109/mwscas.2006.382101
fatcat:apiecrsrhfhxjkdj6x5hu5ca5m
A Clustering Approach for Improving Network Performance in Heterogeneous Systems
[chapter]
2000
Lecture Notes in Computer Science
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Also, we propose a criterion to measure the quality of each one of the possible mappings of processes to processors based on that network partition. ...
In this paper, we propose a clustering algorithm that, given a network topology, provides a network partition adapted to the communication requirements of the applications running on the machine. ...
The proposed algorithm intends to provide a network partition adapted to any existing set of logical clusters. ...
doi:10.1007/3-540-44520-x_170
fatcat:2gmjzxmncbhcnpekm5xbflx5gq
A term-based inverted index partitioning model for efficient distributed query processing
2013
ACM Transactions on the Web
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In practice, the index is either document-based or term-based partitioned. ...
In query processing on retrieval systems that adopt a term-based index partitioning strategy, the high communication overhead due to the transfer of large amounts of data from the index servers forms a ...
Typically, the matching can be performed in two different ways, based on the AND logic (the conjunctive mode) or the OR logic (the disjunctive mode). ...
doi:10.1145/2516633.2516637
fatcat:hkuqmjmbvzakpmc4degshrx26q
Logic emulation with virtual wires
1997
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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However, traditional FPGA-based logic emulators have poor interchip communication bandwidth, commonly limiting gate utilization to less than 20%. ...
Even with crossbar technology, current emulators only use a fraction of potential communication bandwidth because they dedicate each FPGA pin (physical wire) to a single emulated signal (logical wire). ...
As shown in Fig. 14 , these new netlists contain the original design partition along with all necessary virtual wires communication logic. ...
doi:10.1109/43.640619
fatcat:xslresgiivbi7pjbujhtecivii
Logic Emulation with Virtual Wires Manuscript received March 20, 1995; revised April 26, 1996 and June 17, 1997. This work was supported by ARPA Contract N00014-91-J-1698 and NSF Grant MIP-9012773. This paper was recommended by Associate Editor C.-K. Cheng. Publisher Item Identifier S 0278-0070(97)07006-1
[chapter]
2002
Readings in Hardware/Software Co-Design
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However, traditional FPGA-based logic emulators have poor interchip communication bandwidth, commonly limiting gate utilization to less than 20%. ...
Even with crossbar technology, current emulators only use a fraction of potential communication bandwidth because they dedicate each FPGA pin (physical wire) to a single emulated signal (logical wire). ...
As shown in Fig. 14 , these new netlists contain the original design partition along with all necessary virtual wires communication logic. ...
doi:10.1016/b978-155860702-6/50058-2
fatcat:z7simtmezreitcvsypfzt2yf6e
On Scalability and Mobility Management of Hierarchical Large-Scale Ad Hoc Networks
[chapter]
2005
Lecture Notes in Computer Science
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Moreover, we describe a protocol to establish the virtual broadcast domains by using the IPv6 addressing concept in ad hoc networks and perform IP-based network communications in a multi-switch backbone ...
With this characteristic, we propose an interoperability network model integrating self-organizing ad hoc networks and the Internet/a conventional network with the partition of physical/virtual subnets ...
We also discuss an architecture based on a specific logical topology by partitioning a mobile ad hoc network into logically independent subnets. ...
doi:10.1007/11596042_74
fatcat:gsh6bznx6vab5as6eznmjuzag4
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