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Fine-grain multithreading with the EM-X multiprocessor

Andrew Sohn, Yuetsu Kodama, Jui Ku, Mitsuhisa Sato, Hirofumi Sakane, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi
1997 Proceedings of the ninth annual ACM symposium on Parallel algorithms and architectures - SPAA '97  
This report explicates the multithreading capabilities of the EM-X distributed-memory multiprocessor through empirical studies.  ...  Even in the absence of thread computation parallelism, multithreading helps overlap over 3570 of the communication time for bitonic sorting.  ...  This consumption adversely affects the performance, Details are presented in [18], The EM-X multithreaded multiprocessor The EM-X is a multithreaded distributed memory multiprocessor, built and operational  ... 
doi:10.1145/258492.258511 dblp:conf/spaa/SohnKKSSYSY97 fatcat:yxikd7vw5vezrdvo7vwiozgjrq

Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC

Sang-Il Han, Soo-Ik Chae, Lisane Brisolara, Luigi Carro, Ricardo Reis, Xavier Guérin, Ahmed Amine Jerraya
2007 Design automation for embedded systems  
From a system architecture Simulink model, a code generator produces a multithreaded code, inserting thread and communication primitives to abstract the heterogeneity of the target architecture.  ...  In addition, the multithread code generator called LESCEA applies the extensions of dataflow based memory optimization techniques, considering both data and control dependency.  ...  Multithreaded code generation A heterogeneous MPSoC requires complex multithreaded programming such as management of a large number of threads and communications, allocation data memories, distribution  ... 
doi:10.1007/s10617-007-9009-4 fatcat:aeokzqyid5cwbeoh7pukbitghu

Multithreaded Processors

T. Ungerer
2002 Computer journal  
The main approaches are the (single) chip multiprocessor and the multithreaded processor which optimize the throughput of multiprogramming workloads rather than single-thread performance.  ...  The chip multiprocessor integrates two or more complete processors on a single chip. Every unit of a processor is duplicated and used independently of its copies on the chip.  ...  To perform such a remote-memory access in a distributed shared-memory (DSM) multiprocessor, the processor issues a request message to the communication network that couples the processor-memory nodes.  ... 
doi:10.1093/comjnl/45.3.320 fatcat:hlkkabuhrzhkrmuyqomzfmc6zm

Multi-Threaded Processors [chapter]

David Padua, Amol Ghoting, John A. Gunnels, Mark S. Squillante, José Meseguer, James H. Cownie, Duncan Roweth, Sarita V. Adve, Hans J. Boehm, Sally A. McKee, Robert W. Wisniewski, George Karypis (+29 others)
2011 Encyclopedia of Parallel Computing  
The main approaches are the (single) chip multiprocessor and the multithreaded processor which optimize the throughput of multiprogramming workloads rather than single-thread performance.  ...  The chip multiprocessor integrates two or more complete processors on a single chip. Every unit of a processor is duplicated and used independently of its copies on the chip.  ...  To perform such a remote-memory access in a distributed shared-memory (DSM) multiprocessor, the processor issues a request message to the communication network that couples the processor-memory nodes.  ... 
doi:10.1007/978-0-387-09766-4_423 fatcat:heb3n2cfwnbi5nvxv5kvxd2xgm

Multithreading with distributed functional units

B.K. Gunther
1997 IEEE transactions on computers  
Multithreaded processors multiplex the execution of a number of concurrent threads onto the hardware in order to hide latencies associated with memory access, synchronization, and arithmetic operations  ...  The multiple pipeline approach is studied specifically in the Concurro processor architecture-a machine supporting multiple thread contexts and capable of context switching asynchronously in response to  ...  An extreme case of functional unit distribution occurs in a single-chip multiprocessor, where each processing element (PE) on the chip is equipped with both private cache memory and dedicated functional  ... 
doi:10.1109/12.588034 fatcat:bb67gixdrvgmjdeaxnnyjyhb6a

Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading

Jack L. Lo, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen, S. J. Eggers
1997 ACM Transactions on Computer Systems  
This article explores parallel processing on an alternative architecture, simultaneous multithreading (SMT), which allows multiple threads to compete for and share all of the processor's resources every  ...  Multiprocessors (MP) exploit TLP by executing different threads in parallel on different processors.  ...  ACKNOWLEDGMENTS We would like to thank John O'Donnell of Equator Technologies, Inc. and Tryggve Fossum of Digital Equipment Corp. for the source to the Alpha AXP version of the Multiflow compiler.  ... 
doi:10.1145/263326.263382 fatcat:urempgsyi5fmffbfxkr7s6zcju

The MIT Alewife Machine: A Large-Scale Distributed-Memory Multiprocessor [chapter]

Anant Agarwal, David Chaiken, Kirk Johnson, David Kranz, John Kubiatowicz, Kiyoshi Kurihara, Beng-Hong Lim, Gino Maa, Dan Nussbaum
1992 Scalable Shared Memory Multiprocessors  
Acknowledgments The research reported in this paper is fundea by DARPA contract # N00014-87-K-0825, and by grants from the Sloan foundation and IBM.  ...  Generous equipment grants from SUN Microsystems, Digital Equipment Corporation, and Encore are gratefully acknowledged.  ...  Block multithreading allows a single thread to benefit from the maximum performance of the processor.  ... 
doi:10.1007/978-1-4615-3604-8_13 fatcat:7js5232i3naevnf45t4qmrxtb4

OpenMP for Networks of SMPs

Y.Charlie Hu, Honghui Lu, Alan L. Cox, Willy Zwaenepoel
2000 Journal of Parallel and Distributed Computing  
This system enables the programmer to rely on a single, standard, shared-memory API for parallelization within a multiprocessor and between multiprocessors.  ...  A comparison between the thread implementation and the original implementation of TreadMarks shows that using the hardware shared memory within an SMP node significantly reduces the amount of data and  ...  The use of a single address space within a multiprocessor has pluses and minuses. On the positive side, it reduces the number of changes to TreadMarks to support multithreading on a multiprocessor.  ... 
doi:10.1006/jpdc.2000.1658 fatcat:ppnrsalvhvgoflvxthg3cwvlgi

Cooperative multithreading on embedded multiprocessor architectures enables energy-scalable design

P. Schaumont, Bo-Cheng Charles Lai, Wei Qin, I. Verbauwhede
2005 Proceedings. 42nd Design Automation Conference, 2005.  
We propose an embedded multiprocessor architecture and its associated thread-based programming model.  ...  Using a cycle-true simulation model of this architecture, we are able to estimate energy savings for a threaded C program.  ...  A bus connects the four ARM processors with a hardware test-and-set lock to support inter-process communication and synchronization, and a memory interface to access off-chip memory.  ... 
doi:10.1109/dac.2005.193767 fatcat:ysdbhce73zadnpjqv5vyrbxo34

A survey of processors with explicit multithreading

Theo Ungerer, Borut Robič, Jurij Šilc
2003 ACM Computing Surveys  
Unused instruction slots, which arise from latencies during the pipelined execution of single-threaded programs by a contemporary microprocessor, are filled by instructions of other threads within a multithreaded  ...  These processors optimize the throughput of multiprogramming workloads rather than single-thread performance. We distinguish these processors from implicit multithreaded processors  ...  When accessing a nonlocal memory module in a distributed-shared memory system, the memory latency is enhanced by the transfer time through the communication network.  ... 
doi:10.1145/641865.641867 fatcat:u6x7jdmkfvexnm3culskjsoxwi

Multiprocessor simulation using communicating sequential processes

Pranav S. Vaidya, Jaehwan John Lee
2010 International Journal of Computer Aided Engineering and Technology  
This is evident from the fact that most multiprocessor simulators and simulation frameworks are based either on SDES or use some variation of PDES with cooperative multithreading.  ...  Furthermore, we show how this formal description of a multiprocessor system can be mapped to the primitives provided by the Kent C++CSP multithreading library to create a multithreaded multiprocessor simulator  ...  CONCLUSION AND SUMMARY In this paper, we showed how the formal method of Communicating Sequential Processes (CSP) can be used to describe a multiprocessor system and create subsequent multithreaded multiprocessor  ... 
doi:10.1504/ijcaet.2010.029599 fatcat:5wcz3aynzzdtjibtw5blxtxod4

Improving server software support for simultaneous multithreaded processors

Luke K. McDowell, Susan J. Eggers, Steven D. Gribble
2003 Proceedings of the ninth ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '03  
SMT's ability to execute multiple threads simultaneously within a single CPU offers tremendous potential performance benefits.  ...  This evaluation is complicated, since SMT adopts architectural features and operating costs of both its predecessors (uniprocessors and multiprocessors).  ...  Our case-study server stresses both memory allocation and synchronization.  ... 
doi:10.1145/781503.781504 fatcat:3ewwhcryubafbleaaqrq6wf4hq

Improving server software support for simultaneous multithreaded processors

Luke K. McDowell, Susan J. Eggers, Steven D. Gribble
2003 Proceedings of the ninth ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '03  
SMT's ability to execute multiple threads simultaneously within a single CPU offers tremendous potential performance benefits.  ...  This evaluation is complicated, since SMT adopts architectural features and operating costs of both its predecessors (uniprocessors and multiprocessors).  ...  Our case-study server stresses both memory allocation and synchronization.  ... 
doi:10.1145/781498.781504 dblp:conf/ppopp/McDowellEG03 fatcat:he5oz7dmwrbobhpigptv2c43l4

Improving server software support for simultaneous multithreaded processors

Luke K. McDowell, Susan J. Eggers, Steven D. Gribble
2003 SIGPLAN notices  
SMT's ability to execute multiple threads simultaneously within a single CPU offers tremendous potential performance benefits.  ...  This evaluation is complicated, since SMT adopts architectural features and operating costs of both its predecessors (uniprocessors and multiprocessors).  ...  Our case-study server stresses both memory allocation and synchronization.  ... 
doi:10.1145/966049.781504 fatcat:w5yktkfbwjaavbahjhbi6egp3e

Simultaneous multithreading: a platform for next-generation processors

S.J. Eggers, J.S. Emer, H.M. Levy, J.L. Lo, R.L. Stamm, D.M. Tullsen
1997 IEEE Micro  
Acknowledgments We thank John O'Donnell of Equator Technologies, Inc. and Tryggve Fossum of Digital Equipment Corp. for the source to the Alpha AXP version of the Multiflow compiler.  ...  We also thank Jennifer Anderson of DEC Western Research Laboratory for copies of the SpecFP95 benchmarks, parallelized by the most recent version of the SUIF compiler, and Sujay Parekh for comments on  ...  We evaluated simultaneous multithreading on a multiprogramming workload consisting of several single-threaded programs and a group of parallel (multithreaded) applications.  ... 
doi:10.1109/40.621209 fatcat:zmx4yx2flnfazi3b6zdwhavnam
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