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SafeResynth: A new technique for physical synthesis

Kai-hui Chang, Igor L. Markov, Valeria Bertacco
2008 Integration  
We achieve these improvements by performing a series of netlist transformations and re-placements that are individually evaluated for logical soundness (that is, they do not alter the logic functionality  ...  Many published optimizations for physical synthesis end up hurting the quality of the final design, often because they neglect important physical aspects of the layout, such as long wires or routing congestion  ...  For example, new cell locations cannot be evaluated reliably for technology-independent restructuring unless technology mapping is also performed.  ... 
doi:10.1016/j.vlsi.2008.01.004 fatcat:nmi2ofxhdbhgdciefju2hgp7pu

Incremental physical resynthesis for timing optimization

Peter Suaris, Lungtien Liu, Yuzheng Ding, Nanchi Chou
2004 Proceeding of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays - FPGA '04  
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and physical optimizations  ...  and physical optimizations that verifiably improve overall compliance with timing constraints.  ...  INTRODUCTION Timing optimization for FPGA based designs has always been an important aspect, especially because compared with ASIC technology, FPGA technology has a performance disadvantage due to the  ... 
doi:10.1145/968280.968296 dblp:conf/fpga/SuarisLDC04 fatcat:haf7g23yxjex5iogzffalc6tne

Safe Delay Optimization for Physical Synthesis

Kai-hui Chang, Igor L. Markov, Valeria Bertacco
2007 2007 Asia and South Pacific Design Automation Conference  
Many published optimizations for physical synthesis end up hurting the final result, often by neglecting important physical aspects of the layout, such as long wires or routing congestion.  ...  Our resynthesis can also be used in an unsafe mode, akin to more traditional physical synthesis algorithms popular in commercial tools.  ...  technology mapping.  ... 
doi:10.1109/aspdac.2007.358056 dblp:conf/aspdac/ChangMB07 fatcat:ltyw4xfvxnazhnxf32qnzaflqq

IPR

Zhe Feng, Yu Hu, Lei He, Rupak Majumdar
2009 Proceedings of the 2009 International Conference on Computer-Aided Design - ICCAD '09  
Compared to the state-ofthe-art academic technology mapper Berkeley ABC, IPR reduces the relative fault rate by 48% and increases MTTF by 1.94× with the same area and performance, and IPR combined with  ...  a previous fault-tolerant logic resynthesis algorithm (ROSE) reduces the relative fault rate by 49% and increases MTTF by 2.40× with 19% less area but same performance.  ...  Combining IPR and ROSE, the best design flow for reliability and design closure is to perform pre-layout ROSE and post-layout IPR.  ... 
doi:10.1145/1687399.1687422 dblp:conf/iccad/FengHHM09 fatcat:fkyecetprnfgffqx33a3qdx2qu

SynECO: Incremental technology mapping with constrained placement and fast detail routing for predictable timing improvement

Anuj Kumar, Tai-Hsuan Wu, Azadeh Davoodi
2008 2008 IEEE International Conference on Computer Design  
This allows generating timing estimates that correlate much better with post-routing values compared to Steiner-tree-based estimate of wiring tree and using D2M delay model.  ...  Our synthesis framework is completely integrated with the Cadence Encounter tools for physical design.  ...  The main contributions of our work are as follows: • We propose SynECO for physically-aware technology mapping at post-placement stage.  ... 
doi:10.1109/iccd.2008.4751915 dblp:conf/iccd/KumarWD08 fatcat:mkcpr67b25gm3fof5lzlrkxqxe

Scalable don't-care-based logic optimization and resynthesis

Alan Mishchenko, Robert Brayton, Jie-Hong R. Jiang, Stephen Jang
2011 ACM Transactions on Reconfigurable Technology and Systems  
We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability.  ...  Scalable don't-care-based logic optimization and resynthesis.  ...  We thank the anonymous reviewers for their helpful comments.  ... 
doi:10.1145/2068716.2068720 fatcat:h3yagw5jvzc5haolfnzndsiu44

Power-efficient and fault-tolerant circuits and systems

Lei He, Yu Hu
2009 2009 IEEE 8th International Conference on ASIC  
Both increase MTTF by 2X with little or no overhead. Particularly, IPR does not change circuit placement and routing, and can be readily used with the existing industrial design flow.  ...  The ideas presented in the paper can be extend to handle regular logic fabrics, which are natural to nanotechnologies and are also preferred by design for manufacturability (DFM) in scaled CMOS technologies  ...  Boolean matching [14] is one of the most important sub-problems in logic synthesis and technology mapping for FPGAs.  ... 
doi:10.1109/asicon.2009.5351304 fatcat:uw77tpd5dzdqpe55xvj4yrt2ji

Scalable don't-care-based logic optimization and resynthesis

Alan Mishchenko, Robert Brayton, Jie-Hong Roland Jiang, Stephen Jang
2009 Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '09  
We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability.  ...  Scalable don't-care-based logic optimization and resynthesis.  ...  We thank the anonymous reviewers for their helpful comments.  ... 
doi:10.1145/1508128.1508152 dblp:conf/fpga/MishchenkoBJJ09 fatcat:gwh2phiwsfef3juiclxlueaqpy

Understanding and addressing the impact of wiring congestion during technology mapping

Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
2002 Proceedings of the 2002 international symposium on Physical design - ISPD '02  
In this paper we propose a practical, complete methodology which first performs congestion-aware technology mapping using a global weighting factor for the cost function [15] , and then applies incremental  ...  Most importantly, through the application of this methodology to industrial examples we will show that any attempt at a purely top-down single-pass congestion-aware technology mapping is merely wishful  ...  ., Rozzano, Italy, for several enlightening discussions on physical design and continuous support with tools.  ... 
doi:10.1145/505388.505421 dblp:conf/ispd/PandiniPS02 fatcat:kzouehxb65fvvfrumttodwzeie

Understanding and addressing the impact of wiring congestion during technology mapping

Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
2002 Proceedings of the 2002 international symposium on Physical design - ISPD '02  
In this paper we propose a practical, complete methodology which first performs congestion-aware technology mapping using a global weighting factor for the cost function [15] , and then applies incremental  ...  Most importantly, through the application of this methodology to industrial examples we will show that any attempt at a purely top-down single-pass congestion-aware technology mapping is merely wishful  ...  ., Rozzano, Italy, for several enlightening discussions on physical design and continuous support with tools.  ... 
doi:10.1145/505418.505421 fatcat:hl7qj3mxe5abzient4jlyup6ge

Robust FPGA resynthesis based on fault-tolerant Boolean matching

Yu Hu, Zhe Feng, Lei He, Rupak Majumdar
2008 2008 IEEE/ACM International Conference on Computer-Aided Design  
Finally, we show that existing PLB (programmable logic block) templates for area-aware Boolean matching and logic resynthesis are not effective for fault tolerance, and propose a new robust template with  ...  Compared to the state-of-the-art academic technology mapper Berkeley ABC, ROSE using the proposed robust PLB template reduces the fault rate by 25% with 1% fewer LUTs, and increases MTBF (mean time between  ...  It can be performed simultaneously with technology mapping or as a post-mapping optimization.  ... 
doi:10.1109/iccad.2008.4681654 dblp:conf/iccad/HuFHM08 fatcat:i3ngyaawnzcvdffu6kkmbf7z3q

Defect-Aware High-Level Synthesis and Module Placement for Microfluidic Biochips

Tao Xu, Krishnendu Chakrabarty, Fei Su
2008 IEEE Transactions on Biomedical Circuits and Systems  
We present a unified synthesis method that combines defect-tolerant architectural synthesis with defect-aware physical design.  ...  Recent advances in microfluidics technology have led to the emergence of miniaturized biochip devices, also referred to as lab-on-a-chip, for biochemical analysis.  ...  Since we are dealing with multi-objective optimization (chip area, assay time, defect tolerance), we combine simulated annealing algorithm with a genetic algorithm to better represent candidate designs  ... 
doi:10.1109/tbcas.2008.918283 pmid:23852633 fatcat:z6imlaefzvhwhh5ez4lt4hbs5a

Fault-tolerant resynthesis with dual-output LUTs

Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He, Minming Li
2010 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)  
We present a fault-tolerant post-mapping resynthesis for FPGA-based designs that exploits the dual-output feature of modern FPGA architectures to improve reliability of a mapped circuit against faults.  ...  The problem of fault tolerant post-mapping resynthesis is then formulated as the optimal duplication and encoding scheme that ensures minimal circuit fault rate w.r.t. a stochastic single fault model.  ...  As our experiments present the area-robustness-performance tradeoff of the two extreme cases (mapping with 6-LUTs and 5-LUTs), simultaneous technology mapping and resynthesis should be studied in order  ... 
doi:10.1109/aspdac.2010.5419873 dblp:conf/aspdac/LeeHMHL10 fatcat:hgquubo63rgqnhfipv6fvbgjlu

Rewiring for robustness

Manu Jose, Yu Hu, Rupak Majumdar, Lei He
2010 Proceedings of the 47th Design Automation Conference on - DAC '10  
We present R2, an algorithm for rewiring a post-layout LUTbased circuit that reduces the overall criticality of the circuit, where criticality is the fraction of primary inputs that lead to observable  ...  Compared to IPR, a recent robust logic optimization, our implementation increases MTTF (Mean Time to Failure) by 24%, showing for the first time, the advantages of exploiting Boolean flexibilities in optimizing  ...  For example, [18] introduce logic masking by a template with reconvergent paths for technology mapping and resynthesis, and [20] rewrites LUT configuration bits for local logic masking while maintaining  ... 
doi:10.1145/1837274.1837391 dblp:conf/dac/JoseHMH10 fatcat:7pyknrdf6bcjzfrcys6e2dwv2e

Combining Technology Mapping With Layout

Massoud Pedram, Narasimha Bhat, Ernest S. Kuh
1997 VLSI design (Print)  
The two processes are performed in lockstep: technology mapping takes advantage of detailed information about the interconnect delays and the layout cost of various optimization alternatives; placement  ...  more substantial, interconnect optimization must be performed during all phases of the design.  ...  In both cases, the technology-independent optimizations were performed using the MIS program. The benchmarks were optimized for minimum area using the rugged script [24] .  ... 
doi:10.1155/1997/73654 fatcat:6d3j563congtpeabr4is64izva
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