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Page 6 of Automation and Remote Control Vol. 55, Issue 1 [page]

1994 Automation and Remote Control  
Kritter and Rahaga [35] propose an extension of the built-in BS-facilities by the following units (Fig. 6): — built-in test macrocell (BT macrocell), realizing self-test of combinatorial units; it is designed  ...  The advantage of the proposed structure is that it combines the standard approach in integrating the self-test circuits into the BS-architecture, on the one hand, and takes into consideration the individual  ... 

Design for Testability (DFT) for a Chip with Memory and Logic

Pradyumna S Acharya, Sujatha D Badiger
2020 Zenodo  
Memory Built in self-test (MBIST) for memory testing and scan insertion for sequential circuits are the major DFT techniques commonly used.  ...  Faulty chips will reach customer if IC testing is not performed on the fabricated IC. Simple types of testing such as functional and structural testing are not feasible in case of a large circuit.  ...  Common DFT techniques are Scan chain testing, Logic Built in self-test (LBIST) and Memory Built in self-test (MBIST).  ... 
doi:10.5281/zenodo.3898260 fatcat:tggyct76frh2jp3vkzemh7ugpm

Implementation of Huffman data Compression on Multiple Scan Chain BIST

E. Sankari, K. Ramamoorthy
2019 International Journal of Software & Hardware Research in Engineering  
The generation of a test set can be obtained either by algorithmic methods or by pseudo-random methods with a combination of Serial Scan shift register.  ...  Such that immoderate test equipment andsupports field test could be reduced by Built InSelf-Test (BIST).  ...  BUILT IN SELF-TEST Built in Self-Test is a self-testing process it does not required any external hardware equipment. The main aim to test an Integrated circuit whether it is good or bad condition.  ... 
doi:10.26821/ijshre.7.5.2019.7504 fatcat:f3o4qornlzh65evvgwikthlep4

Page 1264 of Automation and Remote Control Vol. 53, Issue 8 [page]

1992 Automation and Remote Control  
INTRODUCTION Widely used methods of ensuring a self-testing and self-checking very large-scale integrated (VLSI) circuits are scanning | 1], built-in self-testing [2], and constrained scanning, which was  ...  DESIGN OF SELF-TESTING AND SELF-CHECKING COMBINATIONAL CIRCUITS WITH WEAKLY INDEPENDENT OUTPUTS M. Goessel and E. S.  ... 

Testing Technique of BIST: A Survey

Sakshi Shrivastava, Paresh Rawat, Sunil Malviya
2017 International Journal of Computer Applications  
This paper gives brief informative review of Built-in Self-test (BIST) and its testing techniques. Recently BIST Research is being highly used in VLSI and SoC testing for the detection fault coverage.  ...  Starting with a broad idea of test problems, this survey paper focus on "Chip" Built in Self-Test (BIST) study and its promotion for board and system-level applications.  ...  Built-in self-test (BIST) is a set of structured-test techniques for combinational and sequential logic, memories, multipliers, and other embedded logic blocks.  ... 
doi:10.5120/ijca2017913133 fatcat:jpajhgrbxncwfnndzezx77bniq

Globally optimized robust systems to overcome scaled CMOS reliability challenges

Subhasish Mitra
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
Three techniques that can enable a sea change in robust system design are: 1. Built-In Soft Error Resilience (BISER), 2. Circuit Failure Prediction, and 3.  ...  Concurrent Autonomous self-test using Stored Patterns (CASP). Global optimization across multiple abstraction layers is essential for cost-effective robust system design using these techniques.  ...  Acknowledgment This research was supported in part by the FCRP Gigascale Systems Research Center (GSRC), FCRP Center for Circuit and System Solutions (C2S2), Semiconductor Research Corporation, and the  ... 
doi:10.1145/1403375.1403603 fatcat:6bysfmqlxrezziegojh6d7ixfy

Methodological Research on Testability Design for Microcontroller

Shui-rong JU, Shuo BAI, Kai-peng GUO, Jia LI, Ling-zhi KONG
2019 DEStech Transactions on Computer Science and Engineering  
Design for testability about calculator circuit SX1702 which based on 4-bit embeded-system are introduced include module division and ROM content testing, this technique provides both controllability and  ...  Acknowledgements This research is supported by the Top-notch Academic Programs Project of Jiangsu Higher Education Institutions(PPZY2015B190),it is also supported by the project of Science and technology  ...  Built in Self Test (BIST) Technology Built in self test technology is a kind of technology put test excitation test result detection in the same chip, using this technology, as long as there is one test  ... 
doi:10.12783/dtcse/aicae2019/31498 fatcat:mczrruwe5bb53j5uduy76dwvi4

An Efficient Implementation of Built in Self Diagnosis for Low Power Test Pattern Generator

N. Nithya
2015 International Journal of Students Research in Technology & Management  
A New architecture of Built-In Self-Diagnosis is presented in this project. The logic Built-In-Self-Test architecture method is extreme response compaction architecture.  ...  The modified Built-In-Self-Test circuit incorporates a fault syndrome compression scheme and improves the circuit speed with reduction of time.  ...  Logic BIST Logic built-in self-test (or LBIST) is a form of built-in self-test (BIST) in which hardware and/or software is built into integrated circuits allowing them to test their own operation, as opposed  ... 
doi:10.18510/ijsrtm.2015.326 fatcat:ahrapsezqrhlje63mbadxyyqzu

Testing the 500-MHz IBM S/390 microprocessor

T.G. Foote, D.E. Hoffman, W.V. Huott, T.J. Koprowski, M.P. Kusko, B.J. Robbins
1998 IEEE Design & Test of Computers  
Programmable memory (RAM) built-in self-test SGC Self-generated clock SI Scan-in SO Scan-out SRL Shift register latch SRSG Shift register sequence generator STCM Self-test control macro STUMPS  ...  nonregister memories are test-ed with a programmable memory built-in self-test engine (RAMBIST).  ...  Kusko is a senior engineer in EDA at IBM, East Fishkill, where she has worked as a consultant in test strategy definition and implementation.  ... 
doi:10.1109/54.706038 fatcat:w3nfhg7wynbbjfgktjiw3gy3iu

Implementation and Utilization of LBIST for 16 bit ALU

2019 VOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE  
This paper refers to implementation of Low Power Built-In-Self-Test (LBIST) and its utilization for testing of 16 bit ALU core.  ...  Low Power Test Pattern (LP) Generator is programmable and able to produce pseudorandom test patterns. The programmability feature brings in selectiveness in toggling levels of test patterns.  ...  BIST (Built In Self-Test) is a method of self-testing. This self-testing can be achieved by providing the design of extra hardware features and software features to the integrated circuit.  ... 
doi:10.35940/ijitee.j9266.0881019 fatcat:liwg4qhquzamzmdycjv2jvjlpa

A programmable built-in self-test core for embedded memories

Chih-T. Huang, Jing-R. Huang, Cheng-W. Wu
2000 Proceedings of the 2000 conference on Asia South Pacific design automation - ASP-DAC '00  
We present a prototype chip for a programmable built-in self-test (BIST) design that is used for testing embedded memories, especially DRAMs.  ...  The BIST chip supports various memory test algorithms by a novel controller and sequencer design.  ...  It is widely believed that built-in self-test (BIST) is the most promising solution to this issue-with BIST, the tester requirement can be minimized, and the tester time can be greatly reduced throughout  ... 
doi:10.1145/368434.368474 dblp:conf/aspdac/HuangHW00 fatcat:cslzpjd3abhmfgol762nxrymya

Design for Testability of Integrated Circuits and Project Protection Difficulties

E. Ph. Pevtsov, T. A. Demenkova, A. A. Shnyakin
2019 Российский технологический журнал  
The solutions include the verification of the correct performance of the manufactured chip by means of external tests and/or self-testing procedures.  ...  for providing test coverings; 4) to provide for the development in projects of special test kits and methods of their generation at the design stage of functions in order to detect malicious nodes and  ...  Acknowledgments The work was carried out within the framework of the state order with the support of the Ministry of Science and Higher Education of the Russian Federation (project № 8.5098.2017/8.9).  ... 
doi:10.32362/2500-316x-2019-7-4-60-70 fatcat:zcj7ligypfetbenu7y75omnruq

A tutorial on built-in self-test. 2. Applications

V.D. Agrawal, C.R. Kime, K.K. Saluja
1993 IEEE Design & Test of Computers  
Acknowledgment The National Science Foundation, Division of Microelectronic Information Processing Systems, under grants MIP-9003292 and MIP-9111886, partially supported this work.  ...  ) thatgeneratesa sequence of test patterns to test faults in a circuit Boundary scan: a method of providing serial scan access to all the inputs and outputs of a device Built-in logic block observer  ...  Its BIST techniques include full serial scan and pseudorandom pattern use in the form of STUMPS. In addition, the system uses embedded RAM self-test and performs delay testing. ~ Table 1 .  ... 
doi:10.1109/54.211530 fatcat:qudfuz5lf5dsre6er623la34nu

A Comparative Study of Low Power Testing Techniques for Digital Circuits

Suhas B Shirol, Rajashekar B Shettar
2017 International Journal of Advanced Research in Computer Science and Software Engineering  
The main focus of the paper is to make a comparative study of low power Linear Feedback Shift Register (LFSR) architecture such as Built In Self Test (BIST), it has been often seen that during test mode  ...  In recent years, with fast growth of mobile communication and portable computing systems, design for low power has become the challenge in the field of Digital VLSI design.  ...  Built In Self Test In modern chip design the complexity is very high, external testing with Automatic Test Equipment(ATE) become extremely expensive.  ... 
doi:10.23956/ijarcsse/v7i7/0180 fatcat:hiimyltyuzhuxoz3fv7qhgfgte

Built-in self-diagnosis targeting arbitrary defects with partial pseudo-exhaustive test

Alejandro Cook, Sybille Hellebrand, Michael E. Imhof, Abdullah Mumtaz, Hans-Joachim Wunderlich
2012 2012 13th Latin American Test Workshop (LATW)  
Index Terms-Built-in Self-Test, Pseudo-Exhaustive Test, Built-in Self-Diagnosis I.  ...  Pseudo-exhaustive test completely verifies all output functions of a combinational circuit, which provides a high coverage of non-target faults and allows an efficient on-chip implementation.  ...  To exploit the benefits of P-PET also for yield ramp-up and in-field repair, it must be combined with efficient techniques for built-in self-diagnosis (BISD).  ... 
doi:10.1109/latw.2012.6261229 dblp:conf/latw/CookHIMW12 fatcat:euao6arpefafxj3l5jvbn4d36e
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