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HW-SW Co-verification of Concurrent Programs

Levente Bajczi
2018 Zenodo  
The co-verification of HW-SW systems is even more challenging for multi-core systems.  ...  On the software side, there have been many successful attempts at creating a verification framework that takes a formal model and verifies whether it conforms to specified criteria.  ...  HW-SW Co-Simulation As presented in [23] , there have been approaches to HW-SW co-verification through simulation.  ... 
doi:10.5281/zenodo.5905600 fatcat:plwwydubqzgrbni6xi6oztu32e

Automated HW/SW Co-Verification of SystemC Designs Using Timed Automata

Paula Herber
2012 it - Information Technology  
Mit der Kombination aus Model Checking und Konformitätstesten erhalten wir ein Framework für die automatisierte HW/SW Co-Verifikation von SystemC Entwürfen mit Hilfe von Timed Automata (VeriSTA).  ...  Das Framework ist voll-automatisch anwendbar und unterstützt den gesamten HW/SW Co-Design Prozess.  ...  The proposed idea to obtain a continuous quality assurance process for HW/SW co-designs by a combination of model checking and testing is shown in Figure 4 .2.  ... 
doi:10.1524/itit.2012.0692 fatcat:r5atkjzrpvdhzpm4tunx2oiovy

HW/SW co-verification of embedded systems using bounded model checking

Daniel Groβe, Ulrich Kühne, Rolf Drechsler
2006 Proceedings of the 16th ACM Great Lakes symposium on VLSI - GLSVLSI '06  
In this paper we present an integrated approach for formal verification of hardware and software. The approach is demonstrated on a RISC CPU. The verification is based on bounded model checking.  ...  In this context formal verification techniques allow to prove the functional correctness. But in embedded system design the integration of software components becomes more and more important.  ...  CONCLUSIONS AND FUTURE WORK In this paper we presented an approach to hardware/software co-verification based on bounded model checking.  ... 
doi:10.1145/1127908.1127920 dblp:conf/glvlsi/GrosseKD06 fatcat:kzgy6cbvefgjblyqtsh2uagube

Unified HW/SW Co-Verification Methodology for High Throughput Wireless Communication System

Nana Sutisna, Reina Hongyo, Leonardo Lanante Jr., Yuhei Nagao, Masayuki Kurosaki, Hiroshi Ochi
2016 IPSJ Transactions on System LSI Design Methodology  
HW/SW co-verification, nowadays, is interesting and practical as a tool for system verification because it allows covering large number of verification scenarios in acceptable time.  ...  In this paper, we present an efficient and unified framework of HW/SW co-verification methodology for large scale system, particularly high throughput wireless communication system.  ...  Unified HW/SW Design To implement a complete design of HW/SW co-verification, first we have to provide a generic architecture for HW/SW implementation, as shown in Fig. 3 .  ... 
doi:10.2197/ipsjtsldm.9.61 fatcat:onwiyrgeevbmbc4uxj4euqiroi

Software-friendly HW/SW Co-Simulation: An Industrial Case Study

J. Noguera, L. Baldez, N. Simon, L. Abello
2006 Proceedings of the Design Automation & Test in Europe Conference  
This paper proposes a novel HW/SW co-simulation approach that minimizes the impact on software designers.  ...  verification and ASIC engineers can help in the SW development).  ...  In other words, we want to provide the SW designers a HW/SW co-simulation environment that enables a smooth integration between their current approach and this new co-development solution.  ... 
doi:10.1109/date.2006.243811 dblp:conf/date/NogueraBSA06 fatcat:eoy7ttz3nndodkdygobkiy62pm

Future Automotive HW/SW Platform Design (Dagstuhl Seminar 19502)

Dirk Ziegenbein, Selma Saidi, Xiaobo Sharon Hu, Sebastian Steinhorst
2020 Dagstuhl Reports  
This report documents the program and the outcomes of Dagstuhl Seminar 19502 "Future Automotive HW/SW Platform Design".  ...  automotive HW/SW platforms, particularly focusing on predictability of systems regarding extra-functional properties, safe integration of hardware and software components and programmability and optimization  ...  Machine Learning in Cyber-Physical Systems We then started talking about uncertainty and the guarantees that can be provided either with machine learning or with other techniques, linking this to model  ... 
doi:10.4230/dagrep.9.12.28 dblp:journals/dagstuhl-reports/ZiegenbeinSHS19 fatcat:gvrg2tj5enh3rnwtvquch54vo4

Software timing analysis using HW/SW cosimulation and instruction set simulator

Jie Liu, Marcello Lajolo, Alberto Sangiovanni-Vincentelli
1998 Proceedings of the sixth international workshop on Hardware/software codesign - CODES/CASHE '98  
Timing analysis for checking satisfaction of constraints is a crucial problem in real-time system design.  ...  In some current approaches, the delay of software modules is precalculated by a software performance estimation method, which is not accurate enough for hard real-time systems and complicated designs.  ...  This work is also supported by Edward A. Lee and the Ptolemy project.  ... 
doi:10.1145/278241.278299 dblp:conf/codes/LiuLS98 fatcat:uepypwl4zzgjvh7o7mu527tf3m

Hybrid Prototyping Methodology for Rapid System Validation in HW/SW Co-Design

Arief Wicaksana, Amir Charif, Caaliph Andriamisaina, Nicolas Ventroux
2019 2019 Conference on Design and Architectures for Signal and Image Processing (DASIP)  
We aim to provide a rapid and flexible system validation solution for HW/SW co-design at various stages of development based on the availability of TLM and RTL implementations.  ...  The proposed methodology allows online and offline performance analysis and debugging for early feedback in HW/SW architecture exploration.  ...  To overcome such a limitation, various techniques in HW/SW co-design with or without hardware models were proposed [2] .  ... 
doi:10.1109/dasip48288.2019.9049195 dblp:conf/dasip/WicaksanaCAV19 fatcat:kxzsxatq6zex7adg2f3llx4vn4

Hyper-acceleration and HW/SW co-verification as an essential part of IBM eServer z900 verification

J. Kayser, S. Koerner, K.-D. Schubert
2002 IBM Journal of Research and Development  
Hardware/software (HW/SW) co-verification can considerably shorten the time required for system integration and bring-up.  ...  in operating software.  ...  Acknowledgments We would like to thank Jeff Ruedinger and Ed McCain for their very helpful editing comments. *Trademark or registered trademark of International Business Machines, Inc.  ... 
doi:10.1147/rd.464.0597 fatcat:us47ragxbndc7gdxvtpluvbmem

Simulation-based HW/SW co-debugging for field-programmable systems-on-chip

Ruediger Willenberg, Paul Chow
2013 2013 23rd International Conference on Field programmable Logic and Applications  
A custom memory logging mechanism enables access to variables in on-chip, offchip and cached memory.  ...  We are presenting SimXMD (Simulation-based eXperimental Microprocessor Debugger), a tool that allows developers to debug microcontroller code and custom hardware simultaneously.  ...  Acknowledgment We thank Xilinx, CMC Microsystems, Embedded Systems Canada (emSYSCAN) and NSERC for supporting our research.  ... 
doi:10.1109/fpl.2013.6645542 dblp:conf/fpl/WillenbergC13 fatcat:uwptubuia5bafneowghochz5hq

Automatic HW/SW Interface Modeling for Scratch-Pad and Memory Mapped HW Components in Native Source-Code Co-simulation [chapter]

Héctor Posadas, Eugenio Villar
2009 IFIP Advances in Information and Communication Technology  
HW accesses are detected at run-time in the native execution and redirected to a target platform model. Thus, native HW/SW co-simulation is performed without any recoding effort.  ...  SW code developed for a target platform is executed in a host computer for fast functional verification and performance estimations.  ...  One of the main problems in native co-simulation is the modeling of HW/SW communication.  ... 
doi:10.1007/978-3-642-04284-3_2 fatcat:b4bzahlambfn3gl2rbk6hg65w4

The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration

Kim Grüttner, Philipp A. Hartmann, Kai Hylla, Sven Rosinger, Wolfgang Nebel, Fernando Herrera, Eugenio Villar, Carlo Brandolese, William Fornaciari, Gianluca Palermo, Chantal Ykman-Couvreur, Davide Quaglia (+2 others)
2013 Microprocessors and microsystems  
In this paper, we discuss the design challenges of today's heterogeneous HW/SW systems regarding power and complexity, both for platform vendors as well as system integrators.  ...  As a result, we propose a reference framework and design flow concept that combines system-level power optimization techniques with platform-based rapid prototyping.  ...  Acknowledgment The authors thank all partners involved in the COMPLEX FP7 European Integrated Project [6] , funded by the European Commission under Grant Agreement 247999.  ... 
doi:10.1016/j.micpro.2013.09.001 fatcat:7a5ycc45m5h7nkjhxhe4u2j7am

HW/SW co-designed processors: Challenges, design choices and a simulation infrastructure for evaluation

Rakesh Kumar, Jose Cano, Aleksandar Brankovicy, Demos Pavlouz, Kyriakos Stavrouz, Enric Gibertx, Alejandro Martinez, Antonio Gonzalez
2017 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)  
HW/SW co-designed processors like Nvidia Denver, are emerging as a promising alternative.  ...  This paper identifies the key challenges that HW/SW codesigned processors face and the basic requirements for a simulation infrastructure targeting these architectures.  ...  ACKNOWLEDGMENTS This work was supported by the Spanish State Research Agency under grants TIN2013-44375-R and TIN2016-75344-R (AEI/FEDER, EU).  ... 
doi:10.1109/ispass.2017.7975290 dblp:conf/ispass/KumarCBPSGMG17 fatcat:h7zmsyabebbhjitopdldmsfadm

Assisting Static Compiler Vectorization with a Speculative Dynamic Vectorizer in an HW/SW Codesigned Environment

Rakesh Kumar, Alejandro Martínez, Antonio González
2016 ACM Transactions on Computer Systems  
This paper proposes to complement the static vectorization with a speculative dynamic vectorizer in a HW/SW co-design processor.  ...  HW/SW co-designed processors provide an excellent opportunity to optimize the applications at runtime.  ...  This section briefly explains how the speculation and recovery mechanism works in the modelled HW/SW co-designed processor.  ... 
doi:10.1145/2807694 fatcat:hozfujte5zgpdebkklkf5k4sae

CHARMS: A Mapping Heuristic to Explore an Optimal Partitioning in HW/SW Co-Design
CHARMS: 하드웨어-소프트웨어 통합설계의 최적 분할 탐색을 위한 매핑 휴리스틱

Olufemi Adeluyi, Jeong-A Lee
2010 Journal of the Korea Society of Computer and Information  
The key challenge in HW/SW co-design is how to choose the appropriate HW/SW partitioning from the vast array of possible options in the mapping set.  ...  In this paper we present a unique and efficient approach for addressing this problem known as Customized Heuristic Algorithm for Reducing Mapping Sets(CHARMS).  ...  The HW/SW co-design Architecture Model usually consists of an Application Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA) as the hardware platform and a General Purpose Processor  ... 
doi:10.9708/jksci.2010.15.9.001 fatcat:dhlvb5fgjnajrpulkfe76f3j4e
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