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An improved fault-tolerant routing algorithm for a Network-on-Chip derived with formal analysis

Zhen Zhang, Wendelin Serwe, Jian Wu, Tomohiro Yoneda, Hao Zheng, Chris Myers
2016 Science of Computer Programming  
This paper describes the discovery of a potential livelock problem through formal analysis on an extension of the link-fault tolerant NoC architecture introduced by Wu et al.  ...  A fault-tolerant routing algorithm in Network-on-Chip (NoC) architectures provides adaptivity for on-chip communications.  ...  Network-on-Chip Architecture and Routing Algorithm A fully functional NoC system has to be fault-tolerant and free of deadlocks.  ... 
doi:10.1016/j.scico.2016.01.002 fatcat:t43j6pvb2vd4hpa32iz4qbqhby

Fully Reliable Dynamic Routing Logic for a Fault-Tolerant NoC Architecture

Abdulaziz Alhussien, Freek Verbeek, Bernard Van Gastel, Nader Bagherzadeh, Julien Schmaltz
2013 Journal of Integrated Circuits and Systems  
A fault-tolerant adaptive wormhole routing function for Networks-on-Chips (NoCs) is presented.  ...  Using formal verification, we have proven 100% reliability up to three faults, i.e., for any combination of three faults our routing logic remains connected, deadlock-free and livelock-free.  ...  In other words, formal verification has been applied for worst-case analysis, i.e., to assess 100% reliability for any combination of three faults.  ... 
doi:10.29292/jics.v8i1.371 fatcat:ugg3yutsnra4jgedptr3fa2cri

Design of Fault-Tolerant and Reliable Networks-on-Chip

Junshi Wang, Masoumeh Ebrahimi, Letian Huang, Axel Jantsch, Guangjun Li
2015 2015 IEEE Computer Society Annual Symposium on VLSI  
A method to design fault-tolerant NoCs comprising of techniques at the link level, the routing level, and the end-to-end level of the communication is presented.  ...  These point techniques are combined together to design fault-tolerant and reliable NoCs.  ...  Fig. 2 : 2 General flow of fault tolerance combine different fault detection and fault-tolerant methods following the general flow shown in Figure 2. The fault-tolerant flow contains four steps.  ... 
doi:10.1109/isvlsi.2015.33 dblp:conf/isvlsi/WangEHJL15 fatcat:5kzmoflwpjdkfi457l3apifi7a

A Network Adaptive Fault-Tolerant Routing Algorithm for Demanding Latency and Throughput Applications of Network-on-a-Chip Designs

Zulqar Nain, Rashid Ali, Sheraz Anjum, Muhammad Khalil Afzal, Sung Won Kim
2020 Electronics  
Simulation results verified that in a fault-free scenario, the proposed solution outperformed a fault-tolerant XY by achieving a lower latency.  ...  Scalability is a significant issue in system-on-a-chip architectures because of the rapid increase in numerous on-chip resources.  ...  Introduction The contracting size of transistors to submicron levels leads to a large number of cores combined onto a chip known as a system-on-a-chip (SoC).  ... 
doi:10.3390/electronics9071076 fatcat:khfdbihiobhijbddol5s6evxhu

Fault-Tolerant Networks-on-Chip Routing With Coarse and Fine-Grained Look-Ahead

Junxiu Liu, Jim Harkin, Yuhua Li, Liam P. Maguire
2016 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Fault tolerance and adaptive capabilities are challenges for modern networks-on-chip (NoC) due to the increase in physical defects in advanced manufacturing processes.  ...  The novelty of the proposed routing algorithms is the weighted path selection strategies, which make near-optimal routing decisions to maintain the NoC system performance under high fault rates.  ...  In [23] , a fault-tolerant routing algorithm for a 2-D mesh NoC system was proposed.  ... 
doi:10.1109/tcad.2015.2459050 fatcat:pcl6pqguizfgzkspv6givh2vo4

FAULT-TOLERANT ROUTING METHODS IN NETWORK ON CHIP

Sudhina K V, Student,Dept. of Information Technology Government Engineering College Bartonhill Trivandrum, Kerala, India
2020 International Journal of Advanced Research in Computer Science  
Different types of faults are affecting the communication.The fault tolerance issue is an essential factor that has a direct impact on the reliability of the system.  ...  Several solutions are dedicated to enhance the fault tolerance, which in turn will increase the reliability of the system. This paper discuss such solution methods and to compare them through table.  ...  The paper is organized as follows. Section 2 includes literature survey on fault tolerant methods on network-onchip. Section 3 describes an analysis of the methods.  ... 
doi:10.26483/ijarcs.v11i3.6528 fatcat:wgvrjslslfd4dlskno2cqezkcq

Hybrid fault tolerant routing algorithm in NoC

Rimpy Bishnoi
2016 Perspectives in Science  
''Proposed hybrid fault tolerant routing'' section is devoted to the explanation of proposed method. ''Analysis'' section analyzes the proposed scheme.  ...  Proposed method is based on the fact that if we use different algorithms for different virtual channels then it would offer fault tolerance by choosing the virtual channel which offers fault free path.  ... 
doi:10.1016/j.pisc.2016.06.028 fatcat:yluk7znnqjcftp3xvkucyqwhmq

An Effective Routing Algorithm to Avoid Unnecessary Link Abandon in 2D Mesh NoCs

Changlin Chen, Sorin D. Cotofana
2013 2013 Euromicro Conference on Digital System Design  
In NoCs where each interconnection between neighboring routers is composed of a pair of unidirectional links, a broken link usually leads to the abandon of the entire interconnection, even if the other  ...  In this paper, we propose a fault tolerant Routing Algorithm (RA) which can efficiently utilize these fault free links when their pair broken links have available misrouting-contour sides.  ...  Simulation results prove that reserving VCs for fault tolerance degrade the system performance obviously even when no fault happens.  ... 
doi:10.1109/dsd.2013.42 dblp:conf/dsd/ChenC13 fatcat:ueca3mgnxnbcppnsbacrd47y24

Traffic-aware reconfigurable architecture for fault-tolerant 2D mesh NoCs

Poona Bahrebar, Dirk Stroobandt
2018 ACM SIGBED Review  
The rerouting approach which is employed in most of the fault-tolerant methods causes the network performance to degrade considerably due to taking longer paths and creating hotspots around the faults.  ...  Considering the increasing demands for real-time systems, the necessity for designing reconfigurable and robust NoCs is even more pronounced.  ...  RELATED WORK Most of the existing fault-tolerant routing methods rely on detour strategies in order to reroute the packets around the faulty region [4] .  ... 
doi:10.1145/3267419.3267423 fatcat:whq6x2oedbdfvfet3exu2okwra

Synthesizing Self-stabilization through Superposition and Backtracking [chapter]

Alex Klinkhamer, Ali Ebnenasir
2014 Lecture Notes in Computer Science  
This paper presents a sound and complete method for algorithmic design of self-stabilizing network protocols.  ...  We have validated the proposed method by creating both a sequential and a parallel implementation in the context of a software tool, called Protocon.  ...  For example, Liu and Joseph [34] provide a method for augmenting fault-intolerant systems with a set of new actions that implement fault tolerance functionalities.  ... 
doi:10.1007/978-3-319-11764-5_18 fatcat:addxt5m3kfb5rmqkct53t4jb7i

Applied Formal Methods – From CSP to Executable Hybrid Specifications [chapter]

Jan Peleska
2005 Lecture Notes in Computer Science  
These include the verification of high-availability database servers, of fault-tolerant computers now operable in the International Space Station, hardware-in-the-loop tests for the novel Airbus A380 aircraft  ...  New requirements with regard to the test of hybrid control systems, the demand for executable formal specifications, as well as the ongoing discussion about the practical applicability of formal methods  ...  I would like to express my gratitude to the organisers and speakers of the 25 Years of CSP event at the London South Bank University, for creating a stimulating conference with numerous interesting -sometimes  ... 
doi:10.1007/11423348_19 fatcat:g23jjlstjvhgnk7fkiek3yefe4

Intelligent Modeling and Verification 2014

Guiming Luo, Xiaoyu Song, Xiaojing Yang, Krishnaiyan Thulasiraman
2014 Journal of Applied Mathematics  
Through an extensive peer-review process, 32 papers were selected for publication in the new special issue. A total of 16 papers describe optimal system modeling.  ...  After the success of the previous special issue Intelligent Modeling and Verification, which was published last year, we are pleased to announce that the new special issue Intelligent Modeling and Verification  ...  In addition, we would like to express our appreciation for the editorial board members of this journal, who provided valuable help and support throughout the preparation of this special issue.  ... 
doi:10.1155/2014/632027 fatcat:qfrhxkghfnccrnjm5mqxygzcjy

A Partial Irregular-Network Routing on Faulty k-ary n-cubes

Michihiro Koibuchi, Tsutomu Yoshinaga, Yasuhiko Nishimura
2006 Automated Software Engineering, IEEE International Conference  
This paper presents a partial irregular-network routing in order to provide a high fault-tolerance in k-ary n-cube networks.  ...  Moreover, the throughput of the proposed deadlockrecovery routing is almost maintained during a dynamic reconfiguration.  ...  To tolerate a hard failure on links or routers. a large number of fault-tolerant routings have been studied on regular topologies, such as k-array n-cubes.  ... 
doi:10.1109/iwias.2006.23 fatcat:5nxqmbk3nbhgbi66klzg76hrbe

Fault-tolerant communication with partitioned dimension-order routers

R.V. Boppana, S. Chalasani
1999 IEEE Transactions on Parallel and Distributed Systems  
AbstractÐThe current fault-tolerant routing methods require extensive changes to practical routers such as the Cray T3D's dimension-order router to handle faults.  ...  fault-tolerant routing.  ...  This work was performed while Suresh Chalasani was with the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison.  ... 
doi:10.1109/71.808144 fatcat:bajmiqhazjd4zabersidjsr7rm

Scalable dynamic information flow tracking and its applications

Rajiv Gupta, Neelam Gupta, Xiangyu Zhang, Dennis Jeffrey, Vijay Nagarajan, Sriraman Tallam, Chen Tian
2008 Proceedings, International Parallel and Distributed Processing Symposium (IPDPS)  
The focus of our ongoing work is on developing online dynamic analysis techniques for long running multithreaded programs that may be executed on a single core or on multiple cores to exploit thread level  ...  ), and data validation (lineage tracing of scientific data).  ...  Given the fact that lineage sets could be as large as thousands of elements, the extended DIFT system is capable of tracing data lineage with cost that can be tolerated in the context.  ... 
doi:10.1109/ipdps.2008.4536382 dblp:conf/ipps/GuptaGZJNTT08 fatcat:adkkludfwvdejkfra3mitwlmiq
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