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Combined Frame Memory Motion Compensation for Video Coding

N.Y.-C. Chang, Tian-Sheuan Chang
2006 IEEE transactions on circuits and systems for video technology (Print)  
We proposed a non-combined frame memory motion compensation (CFMMC) for video decoding which facilitates the characteristic of the perfect-matched macroblock (MB) to avoid unnecessary memory access and  ...  The frame memory has long been the dominant component in a video decoder in terms of energy, area, and latency.  ...  Architecture of the Combined Frame Memory Motion Compensation The architecture of the CFMMC is illustrated in Fig. 4 , which consists of five major parts.  ... 
doi:10.1109/tcsvt.2006.881867 fatcat:syninkhcwjhjrecykvmetagoxa

Parallel implementation of Multi-view Video Decoder for Reduction in Power Consumption

Xiang JunZhao, Yeon-Man Jeong, Yong Beom Cho
2012 International Journal of Computer Applications  
In existing implementations, multi-processor based architectures have been employed to achieve real-time processing in H.264/AVC. In this paper, a parallel MVC decoding scheme is presented.  ...  Multi-view coding (MVC) is an extension of H.264/AVC scheme employed for high performance compression of multi view videos.  ...  Proposed MVC decoder architecture In [4] , it was shown that for single view-point videos stream the MC is performed in GPU.  ... 
doi:10.5120/9374-3847 fatcat:ribspitc3rbttc2bp6f75mmwle

A novel embedded bandwidth-aware frame compressor for mobile video applications

Yu-De Wu, Yao Li, Chen-Yi Lee
2009 2008 International Symposium on Intelligent Signal Processing and Communications Systems  
To reduce the bandwidth requirement and the size of frame memory for video decoding, embedding a compressor/decompressor on the chip is a well-known solution.  ...  With pipelined architecture, it takes 72 cycles and 34 cycles per MB for encoding and decoding respectively.  ...  But to accomplish this method when encoding or decoding, at least one previous frame must be stored in frame memory as reference.  ... 
doi:10.1109/ispacs.2009.4806703 fatcat:u3puqod5wvfnlkbrab37ls2jqa

Application Specific Processor Design for H.264 Decoder with a Configurable Embedded Processor

Jin Ho Han, Mi Young Lee, Younghwan Bae, Hanjin Cho
2005 ETRI Journal  
The motion compensation, inverse integer transform, inverse quantization, and entropy decoding algorithm of H.264 decoder software are optimized.  ...  An application specific processor for an H.264 decoder with a configurable embedded processor is designed in this research.  ...  First, we developed an H.264 video decoder for a baseline profile at level 2 in C language. The video format is CIF 15 frames/sec.  ... 
doi:10.4218/etrij.05.0905.0001 fatcat:ohemqmxb6fa5foxqnfljzdq7vm

Accelerating wavelet-based video coding on graphics hardware using CUDA

W.J. van der Laan, J.B.T.M. Roerdink, A.C. Jalba
2009 2009 Proceedings of 6th International Symposium on Image and Signal Processing and Analysis  
We have integrated our DWT into the Dirac Wavelet Video Codec (DWVC), of which the overlapped block motion compensation compensation and frame arithmetic have been accelerated using CUDA as well.  ...  This transform, by means of the lifting scheme, can be performed in a memory and computation efficient way on modern, programmable GPUs, which can be regarded as massively parallel co-processors through  ...  [10] , with the aim to provide an architecture for video coding on the GPU, with special focus on the motion compensation and frame arithmetic parts.  ... 
doi:10.1109/ispa.2009.5297658 fatcat:fb2fu2g5efcvhdfbsw35nulize

A 135 MHz 542 k Gates High Throughput H.264/AVC Scalable High Profile Decoder

Gwo-Long Li, Yu-Chen Chen, Yuan-Hsin Liao, Po-Yuan Hsu, Meng-Hsun Wen, Tian-Sheuan Chang
2012 IEEE transactions on circuits and systems for video technology (Print)  
For texture padding in interlayer intra prediction, the modified padding flow can save 26% of decoding time.  ...  For decoding flow, this paper proposes an one-pass macroblock-based quality layer decoding flow for SNR scalability and 71% of external memory bandwidth and 66% of macroblock processing cycles can be saved  ...  : The high memory bandwidth requirement in motion compensation is also the bottleneck in a video decoder design.  ... 
doi:10.1109/tcsvt.2011.2171213 fatcat:d5pxven3wnbptny32jmijodflm

End-to-end Neural Video Coding Using a Compound Spatiotemporal Representation [article]

Haojie Liu, Ming Lu, Zhiqi Chen, Xun Cao, Zhan Ma, Yao Wang
2021 arXiv   pre-print
Recognizing that each resampling solution offers unique advantages in regions with different motion and texture characteristics, we propose a hybrid motion compensation (HMC) method that adaptively combines  ...  In spite of the great success of adaptive kernel-based resampling (e.g., adaptive convolutions and deformable convolutions) in video prediction for uncompressed videos, integrating such approaches with  ...  Here, we warping SFE (a) Vector-based motion decoder (b) Adaptive kernel-based motion decoder (c) Compensation mode decoder (d) Texture enhancement decoder Fig. 7 : Network Architecture for the Independent  ... 
arXiv:2108.04103v1 fatcat:u43qnoz5pfgmvo3lwsmvr4kk4m

Memory Performance Optimizations For Real-Time Software HDTV Decoding

Han Chen, Kai Li, Bin Wei
2005 Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology  
We then describe an algorithm to explic-64 itly prefetch macroblocks for motion compensation.  ...  Second, the paper describes an algorithm to explicitly prefetch macroblocks for motion compensation.  ...  For example, in 472 MPEG-2 video decoding, when motion compensation 473 is being performed, 16 × 16-size pixel blocks are read 474 and written at once.  ... 
doi:10.1007/s11265-005-6650-7 fatcat:ak3cwkplijc35k3ez6oukibfta

Accelerating Mobile Video: A 64-Bit SIMD Architecture for Handheld Applications

N. C. Paver, M. H. Khan, B. C. Aldrich, C. D. Emmons
2005 Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology  
Providing quality mobile video applications in hand-held mobile devices requires increased computational capability.  ...  Using Single Instruction Multiple Data (SIMD) techniques to expose and accelerate the data parallelism inherent in video processing increases performance in handheld and wireless systems.  ...  Acknowledgments We acknowledge the significant contribution of the entire Wireless MMX technology development team in Austin, TX, Chandler, AZ and the systems engineering in Hudson, MA.  ... 
doi:10.1007/s11265-005-6248-0 fatcat:cxl5oizairhvpeodacy2rpcnbu

Processor Architectures for Multimedia [chapter]

Borko Furht
1998 Multimedia Technologies and Applications for the 21st Century  
Block 4: Motion Compensation The worst-case scenario is that all blocks in a P-frame are motion compensated with 4-pixel interpolation and all blocks in a B-frame are motion compensated with 8-pixel interpolation  ...  Adding complexities for P-and B-frames, the complexity for motion compensation becomes 273.7 MOPS.  ... 
doi:10.1007/978-0-585-28767-6_1 fatcat:bewu4c7wgncvxjk7eiu6tbpnde

Multidimensional transcoding for adaptive video streaming

Jens Brandt, Lars Wolf, Paal Halvorsen
2009 ACM SIGMultimedia Records  
In this paper we present a multidimensional transcoding approach for MPEG-4 encoded video, which smartly combines existing transcoding techniques to enable fine grain adaptation for different video devices  ...  One approach for video adaptation is the use of video transcoding techniques, where modifications of the video stream are done in the compressed domain to save processing power.  ...  However, in most digital video formats motion compensation is used to utilize temporal dependencies between frames for compression.  ... 
doi:10.1145/1738921.1738926 fatcat:qfbtwzwpy5hhzpm3dqykrbiu64

Memory Analysis of Low Power MPEG-4 Decoder Architecture

Andreas Dahlin, Johan Ersfolk, Haitham Habli, Johan Lilius
2009 2009 International Conference on Embedded Software and Systems  
In this paper we analyse the approach for its memory requirements, and propose some optimisations that will substantially decrease the memory bandwidth of the approach. 2009 International Conferences on  ...  The reason has been attributed to overheads in software, and in the context of multi-media codecs a new approach has been proposed.  ...  The additional memory reads for inter-coded frames originates from the motion compensation operation, in which one or two reference frames must be accessed in order to produce a motion compensated macroblock  ... 
doi:10.1109/icess.2009.85 dblp:conf/icess/DahlinEHL09 fatcat:tgjuequvdbgzbafxmkguy5h7ke

Design and Implementation of a Multithreaded High Resolution MPEG4 Decoder on Sandblaster DSP

Vaidyanathan Ramadurai, Sanjay Jinturkar, Mayan Moudgill, John Glossner
2007 2007 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia  
In this paper, we describe the design, implementation and multithreading of a MPEG 4 decoder (simple profile) for high resolution (VGA 640x480) on Sandblaster DSP.  ...  We describe the multithreading of time critical tasks that are processor intensive as well as memory intensive.  ...  For e.g. motion compensation (MC) is memory-intensive as it operates on current frame/pixels and reference frame/pixels.  ... 
doi:10.1109/estmed.2007.4375806 dblp:conf/estimedia/RamaduraiJMG07 fatcat:suk26n57cfc3fedsnqztzjaxtq

Design of a 125μW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications

Tsu-Ming Liu, Ching-Che Chung, Chen-Yi Lee, Ting-An Lin, Sheng-Zen Wang
2006 Proceedings of the 43rd annual conference on Design automation - DAC '06  
A design of MPEG-2 and H.264/AVC video decoder is demonstrated in a 0.18µm CMOS [1]. The key design issues involved in this advanced IC are discussed, including improving area and power efficiency.  ...  Power dissipation is greatly lowered through the architectural exploration.  ...  Two 4MB external frame memories are connected to SDRAM interface (I/F) via a 64-bit system bus. Accessing SDRAM is issued by both motion compensation and deblocking filter.  ... 
doi:10.1145/1146909.1146984 dblp:conf/dac/LiuCLLW06 fatcat:gwtqar63yrallhugsw56fmw4mm

Design and FPGA prototyping of a H: 264/AVC main profile decoder for HDTV

Luciano V. Agostini, Arnaldo P. Azevedo Filho, Wagston T. Staehler, Vagner S. Rosa, Bruno Zatt, Ana Cristina M. Pinto, Roger Endrigo Porto, Sergio Bampi, Altamiro A. Susin
2007 Journal of the Brazilian Computer Society  
, intra prediction, motion compensation and deblocking filter, for a main profile H.264/AVC decoder.  ...  The post place-and-route synthesis results indicate that the designed architectures are able to process 114 million samples per second and, in the worst case, they are able to process 64 HDTV frames (1080x1920  ...  Motion compensation architecture consists of the motion vector prediction, frame memory access and the sample processing. Motion vectors for neighboring partitions are often highly correlated.  ... 
doi:10.1590/s0104-65002007000100004 fatcat:5xnihia4d5d7ta4gs6n55okjnu
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