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The Programmable Data Plane

Oliver Michel, Roberto Bifulco, Gábor Rétvári, Stefan Schmid
2021 ACM Computing Surveys  
This survey presents recent trends and issues in the design and implementation of programmable network devices, focusing on prominent abstractions, architectures, algorithms, and applications proposed,  ...  Programmable data plane technologies enable the systematic reconfiguration of the low-level processing steps applied to network packets and are key drivers toward realizing the next generation of network  ...  Acknowledgments The research leading to these results has received funding from the European Union's H2020 Framework Programme (H2020-EU.2.1.1) under grant agreement n. 101017171 (Project "Marsal") and  ... 
doi:10.1145/3447868 fatcat:hafeovivhfgmpecqzrinsbfmnq

High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs [chapter]

Rolf Enzler, Tobias Jeger, Didier Cottet, Gerhard Tröster
2000 Lecture Notes in Computer Science  
Consequently, the desire emerges for early performance estimation in order to quantify the FPGA approach and to compare it with traditional alternatives.  ...  The goal is to provide a means that allows early quantification of an FPGA design and that enables early trade-off considerations.  ...  The basic idea behind the concept is to separate the algorithm description from the influence of the FPGA architecture.  ... 
doi:10.1007/3-540-44614-1_57 fatcat:ic3bfh3q2jbqlkopts4sp6uewa

Revisiting the High-Performance Reconfigurable Computing for Future Datacenters

Qaiser Ijaz, El-Bay Bourennane, Ali Kashif Bashir, Hira Asghar
2020 Future Internet  
The purpose is to emphasize the importance of choosing appropriate communication architecture, virtualization technique and standard language to evolve the multi-tenant FPGAs in datacenters.  ...  The sustainability of this large-scale integration depends on enabling multi-tenant FPGAs.  ...  The authors would also like to thank Usman Ahmad, Dalhousie University of Canada for his advice on research writing in general.  ... 
doi:10.3390/fi12040064 fatcat:zrt5ergxnvezlmltkbwgiixcm4

A temporal bipartitioning algorithm for dynamically reconfigurable FPGAs

E. Canto, J.M. Moreno, J. Cabestany, I. Lacadena, J.M. Insenser
2001 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Index Terms-DRFPGA, dynamically reconfigurable FPGA, FIPSOC, temporal bipartitioning.  ...  This paper will describe a systematic method to map synchronous digital systems into dynamically reconfigurable programmable logic (i.e., programmable logic able to swap in real time the configuration  ...  A new scheme for reconfiguring DMCs was introduced to the FIPSOC circuitry enabling a fast reconfiguration time.  ... 
doi:10.1109/92.920836 fatcat:nuesq2iucndfxbyo653qlej5y4

Field-Programmable Gate-Array-Based Graph Coloring Accelerator

L. M. Pochet, M. L. Linderman, S. L. Drager, R. L. Kohler
2002 Journal of Spacecraft and Rockets  
The algorithm developed was tailored to match the underlying FPGA architecture. Algorithm Overview A high-level flow diagram of the graph coloring algorithm process is shown in Fig. 2.  ...  One approach compiles the FPGA to solve a specific problem instance.* This approach attempts to optimize execution speed, but it must first compile the instance before solving it.  ... 
doi:10.2514/2.3852 fatcat:vlgv4kxag5axjkumz7eddbdsta

System-level Scheduling on Instruction Cell Based Reconfigurable Systems

Ying Yi, I. Nousias, M. Milward, S. Khawam, T. Arslan, I. Lindsay
2006 Proceedings of the Design Automation & Test in Europe Conference  
The results show that schedules using this approach achieve equivalent throughput to VLIW architectures but at much lower power consumption.  ...  Unlike other typical scheduling methods, it considers the placement and routing effect, register assignment and advanced operation chaining compilation technique to generate higher performance scheduled  ...  Algorithm CRS Scheduling Input: Assembly Code representing operations to schedule, Space machine description (resource, clock cycle), Routing delay generated by VPR algorithm; Output: Fast and parallel  ... 
doi:10.1109/date.2006.243762 dblp:conf/date/YiNMKAL06 fatcat:dwh5mbmy3jdo5krzxw5z6evvwq

Benchmarking Test-Time Unsupervised Deep Neural Network Adaptation on Edge Devices [article]

Kshitij Bhardwaj, James Diffenderfer, Bhavya Kailkhura, Maya Gokhale
2022 arXiv   pre-print
) the process must not only be fast but also memory- and energy-efficient.  ...  We find that the approach that only updates the normalization parameters with Wide-ResNet, running on Xavier GPU, to be overall effective in terms of balancing multiple cost metrics.  ...  We conclude the paper with some architecture-algorithm insights gained from this study. II.  ... 
arXiv:2203.11295v1 fatcat:xqoam3of25ckdmynndxin2yypi

Configuration and Programming of Heterogeneous Multiprocessors on a Multi-FPGA System Using TMD-MPI

Manuel Saldana, Daniel Nunes, Emanuel Ramalho, Paul Chow
2006 2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006)  
The penalty is the loss of generality in the architecture, but reconfigurability of FPGAs allows them to be reprogrammed for other applications.  ...  Recent research has shown that FPGAs have true potential to speedup demanding applications even further than what state-of-the art superscalar processors can do.  ...  CONACYT in Mexico provided funding to Manuel Saldaña. Thanks to Amirix for the help with their hardware and tools.  ... 
doi:10.1109/reconf.2006.307779 dblp:conf/reconfig/SaldanaNRC06 fatcat:ganr7p2aibhhbgpcf7f55etmmy

Fixed-point trigonometric functions on FPGAs

Florent de Dinechin, Matei Istoan, Guillaume Sergent
2014 SIGARCH Computer Architecture News  
The first approach is the classical CORDIC iteration, for which we suggest a reduced iteration technique and fine optimizations in datapath width and latency.  ...  Three approaches for computing sines and cosines on FP-GAs are studied in this paper, with a focus of highthroughput pipelined architecture, and state-of-the-art implementation techniques.  ...  A TABLE-AND DSP-BASED PARALLEL POLYNOMIAL ARCHITECTURE Algorithm Here we further split our octant angle y into its a most significant bits t, and its lower bits y red ∈ [0, 2 −(2+a) ).  ... 
doi:10.1145/2641361.2641375 fatcat:67bz4akks5f4hamluydwo5tmfy

A Lightweight System-On-Chip Based Cryptographic Core for Low-Cost Devices

Dennis Agyemanh Nana Gookyi, Kwangki Ryoo
2022 Sensors  
The lightweight cryptographic SoC is tested by designing a desktop software application to serve as an interface to the hardware.  ...  The hardware architectures use the concept of resource sharing to minimize the hardware area.  ...  The PRESENT encryption/decryption algorithm is a Substitution-Permutation (SP) network architecture algorithm that encrypts/decrypts a block of 64-bit data in 31 rounds.  ... 
doi:10.3390/s22083004 pmid:35458989 pmcid:PMC9030163 fatcat:lwqegt3a55gjtdfirp4unwabra

A Survey on Deep Packet Inspection for Intrusion Detection Systems [article]

Tamer AbuHmed, Abedelaziz Mohaisen, DaeHun Nyang
2008 arXiv   pre-print
Fundamentally, almost intrusion detection systems have the ability to search through packets and identify contents that match with known attacks.  ...  [40] : TCAM CAM Content Addressable Memory FPGA Network Processors(NP) DPI Implementation Hardware Software SNORT Bro Table 1 . 1 Comparison between Existing Architectures Algorithm  ...  In [12] , new work has been introduced by Chris et al. as a combination between IXP network processors and Xilinx Virtex FPGAs to build IDS.  ... 
arXiv:0803.0037v1 fatcat:5smjxqskfrejnity326r6rjxgu

Time and Energy Efficient Matrix Factorization Using FPGAs [chapter]

Seonil Choi, Viktor K. Prasanna
2003 Lecture Notes in Computer Science  
Our designs on the FPGAs are significantly more time and energy efficient in both cases.  ...  A linear array architecture is employed to minimize the usage of long interconnects, leading to lower energy dissipation.  ...  To perform a computation for the smaller blocks, the architecture/algorithm in Theorem 1 is re-used. By varying the block size, we achieve time and energy efficient designs.  ... 
doi:10.1007/978-3-540-45234-8_50 fatcat:fm7rkh4du5htdkjyecwalvplvi

GRAPE-6: A Petaflops Prototype [article]

Piet Hut, Jeffrey M. Arnold, Junichiro Makino, Stephen L.W. McMillan,, Thomas L. Sterling
1997 arXiv   pre-print
FPGA-based systems can restore the balance, guaranteeing scalability from the teraflops to the petaflops domain, while still retaining significant flexibility. (abbreviated abstract)  ...  It is not cost-effective to attempt to design custom chips for each new problem that arises.  ...  The best of all worlds, however, is to combine the two approaches.  ... 
arXiv:astro-ph/9704183v1 fatcat:23pxshuc3nc2fotn7zmwtervgu

Real-Time Simulation of Passage-of-Time Encoding in Cerebellum Using a Scalable FPGA-Based System

Junwen Luo, Graeme Coapes, Terrence Mak, Tadashi Yamazaki, Chung Tin, Patrick Degenaar
2016 IEEE Transactions on Biomedical Circuits and Systems  
Our design is shown to outperform three alternative approaches previously used for implementing spiking neural network model.  ...  Index Terms-Cerebellum, field-programmable gate array (FPGA), network on chip (NoC), neural-rehabilitation, passage-of-time (POT).  ...  Neurogrid employs a smart approach to combine analogue circuits for mimicking neural process and digital circuits for implementing routing components.  ... 
doi:10.1109/tbcas.2015.2460232 pmid:26452290 fatcat:qh24oq67d5dzfocolwcwmarvi4

Reducing dynamic power consumption in next generation DS-CDMA mobile communication receivers

V. Chandrasekhar, F. Livingston, J.R. Cavallaro
2008 International Journal of Embedded Systems  
The combined effect of reduced precision and complexity reduction leads to a 37.44% power savings.  ...  We then present and analyse two architectures for implementing the reference and reduced complexity receivers, with respect to dynamic power dissipation.  ...  The resulting power-performance profiles have been obtained after passing synthesised complex receiver data simulating a urban three path fading channel through the targeted architectures. • Algorithm  ... 
doi:10.1504/ijes.2008.020294 fatcat:35iujc5cjjfavleg7zi2y75oee
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