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Demonstration of a Time-predictable Flight Controller on a Multicore Processor
2019
2019 IEEE 22nd International Symposium on Real-Time Distributed Computing (ISORC)
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Often, real-time requirements are needed when they are deployed for critical missions. The increasing computational demand for drones leads to a shift towards multicore architectures. ...
We provide timing analysis of the system, and test it with a processor-in-the-loop setup, which includes a flight simulator connected to the flight controller running on a time-predictable multicore platform ...
Acknowledgement The work was partially funded by the Danish Council for Independent Research | Technology and Production Sciences under the project PREDICT (http://predict.compute.dtu.dk/), contract no ...
doi:10.1109/isorc.2019.00029
dblp:conf/isorc/BarisMSCSBS19
fatcat:vzgw7meytzbcfm7f62q4bpm43e
Tuning pipelined scientific data analyses for efficient multicore execution
2016
2016 International Conference on High Performance Computing & Simulation (HPCS)
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weight, and (iii) manages the parallel execution of the computational tasks in a multicore system, applied to the same or to different dataset elements. ...
Preliminary results show an impressive performance improvement of the pipeline tuning when compared to the original sequential HEP code (up to a 35x speedup in a dual 12-core system), and also show significant ...
The first approach uses a sequential code for the data setup and a parallel approach to process events from separate files at each core of a shared memory environment at a multicore system; each thread ...
doi:10.1109/hpcsim.2016.7568410
dblp:conf/ieeehpcs/PereiraOP16
fatcat:k75wmlyoovbsvmyhoaxtwu3jkq
Trace-based performance analysis framework for heterogeneous multicore systems
2010
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)
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interactions Most tracing tools are designed for homogeneous multicore systems and platform-dependent Our goals:Develop a portable toolkit for embedded heterogeneous multicore platform Ported our toolkit ...
The complexity of Today's computer systems have increased with the advent of embedded heterogeneous multicore systems A good application developer has to be familiar with the heterogeneity
Pre-Processing ...
doi:10.1109/aspdac.2010.5419926
dblp:conf/aspdac/HungTS10
fatcat:7mfcexgws5g37dku46ezrhxixu
Multicore development environment for embedded processor in arduino IDE
2020
TELKOMNIKA (Telecommunication Computing Electronics and Control)
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Embedded processors as the core of the IoT system approaches the need for computation by employing a parallel processor system, namely MPSoC. ...
There is a need for such a platform to facilitate both the study and development of parallel embedded software. arduino as the widely used embedded development platform is yet to officially support multicore ...
This demands for hardware capable for complex computations while still maintaining the low-power characteristic of IoT [7, 8] . ...
doi:10.12928/telkomnika.v18i2.14873
fatcat:evtjwtnf5zcvbkn4hbvirnnwxe
Support for the logical execution time model on a time-predictable multicore processor
2016
ACM SIGBED Review
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In this work, we extend a multicore operating system running on a timepredictable multicore processor to support the LET model. ...
For communication between tasks we use message passing on a timepredictable network-on-chip to avoid the bottleneck of shared memory. ...
execution times of important code parts (kernel executed from ISPM) min max send command 429 675 recv command 751 836 adv check 159 273 adv DMA setup 533 751 ...
doi:10.1145/3015037.3015047
fatcat:65x7ewyknjello7mmd7khnlmgy
A software-based root-of-trust primitive on multicore platforms
2011
Proceedings of the 6th ACM Symposium on Information, Computer and Communications Security - ASIACCS '11
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In this paper, we analyze the challenges of designing softwarebased root-of-trust on multicore platforms and present two practical attacks that utilize the parallel computing capability to break the existing ...
We then propose a timing-based primitive, called MT-SRoT, as the first step towards software-based root-oftrust on multicore platforms. ...
The correctness of root-of-trust setup is ensured by the chosen computationally hard problems. ...
doi:10.1145/1966913.1966957
dblp:conf/ccs/YanHLDL11
fatcat:xpbk647hmneavpkajvqhq3plqu
Performance Evaluation of MPI, UPC and OpenMP on Multicore Architectures
[chapter]
2009
Lecture Notes in Computer Science
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Therefore, up-to-date performance evaluations of current options for programming multicore systems are needed. ...
of data locality, the key factor for performance in these systems. ...
We gratefully thank Jim Bovay and Brian Wibecan at HP for their valuable support, and CESGA for providing access to the Finis Terrae supercomputer. ...
doi:10.1007/978-3-642-03770-2_24
fatcat:c4crntkoqrelhp4yxov7aee2ii
Challenges of Scaling Algebraic Multigrid Across Modern Multicore Architectures
2011
2011 IEEE International Parallel & Distributed Processing Symposium
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Algebraic multigrid (AMG) is a popular solver for large-scale scientific computing and an essential component of many simulation codes. ...
However, when executed on modern multicore architectures, we face new challenges that can significantly deteriorate AMG's performance. ...
However, the emergence of multicore architectures in highperformance computing has forced a re-examination of the hypre library and the BoomerAMG code. ...
doi:10.1109/ipdps.2011.35
dblp:conf/ipps/BakerGSY11
fatcat:vopsrrkjcjcslczrq4ltj573ue
A Performance Evaluation of A Parallel Biological Network Microcircuit in Neuron
2013
International Journal of Distributed and Parallel systems
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In this paper we analyse the performance of a CA1neural network microcircuit model for pattern recognition. ...
Moreover, we investigate its scalability andbenefits on multicore and on parallel and distributed architectures. ...
INTRODUCTION Prototyping and developing computational codes of biological networks, in terms of reliability, efficient, and portable building blocks allow to the computational neuroscientists to simulate ...
doi:10.5121/ijdps.2013.4102
fatcat:t5a5m6vp2fbdrj2wwar6ewyfaq
PowerPack: Energy Profiling and Analysis of High-Performance Systems and Applications
2010
IEEE Transactions on Parallel and Distributed Systems
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Energy efficiency is a major concern in modern high-performance computing system design. ...
In this work, we extend our framework to support systems with multicore, multiprocessor-based nodes, and then provide in-depth analyses of the energy consumption of parallel applications on clusters of ...
As in the other measured codes, the energy consumption under the UP setup is larger than that under the CMP setup for a given number of computing cores. FT and IS belong to type III. ...
doi:10.1109/tpds.2009.76
fatcat:rnakwen5jjdijleueilj4vwkg4
On the Performance of an Algebraic Multigrid Solver on Multicore Clusters
[chapter]
2011
Lecture Notes in Computer Science
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Multicore clusters, however, present new challenges for libraries such as hypre, caused by the new node architectures: multiple processors each with multiple cores, sharing caches at different levels, ...
We have implemented most of the techniques in a MultiCore SUPport library (MCSup), which helps to map OpenMP applications to multicore machines. ...
for highly asynchronous codes on multicore platforms; -A MultiCore SUPport (MCSup) library that provides efficient support for mapping an OpenMP program onto the underlying architecture; -A demonstration ...
doi:10.1007/978-3-642-19328-6_12
fatcat:ttxx2zscd5c7lkxkicbjx3gtpa
Comparison of parallelization strategies for min-sum decoding of irregular LDPC codes
2013
Tsinghua Science and Technology
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The first implements min-sum LDPC decoders on multicore platforms using OpenMP, while the other uses the Compute Unified Device Architecture (CUDA) to parallelize LDPC decoding on Graphics Processing Units ...
Low-Density Parity-Check (LDPC) codes are powerful error correcting codes. ...
Introduction With the development of advanced computer hardware technologies, multicore architectures are offering powerful computing platforms for different highperformance computation applications in ...
doi:10.1109/tst.2013.6678903
fatcat:ags3raehhjgyhmbwrik34vgh24
Evaluation of a Feature Tracking Vision Application on a Heterogeneous Chip
2014
2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing
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The challenge with these computationally demanding applications is to execute them efficiently. ...
Consumers of personal devices such as desktops, tablets, or smart phones run applications based on image or video processing, as they enable a natural computer-user interaction. ...
We also thank Mert Dikmen for the help on the early stages of this work. ...
doi:10.1109/sbac-pad.2014.45
dblp:conf/sbac-pad/GranSTG14
fatcat:4hsfgilfb5fynaupazelxjlpcy
Impact of Parallelism on Dualcore
2016
International Journal of Computer Applications
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General Terms Parallel and distributed computing. ...
This paper shows the effect of parallelism in multicore architecture. ...
Fig 1 . 1 Multicore Architecture
depends on the ratio of the amount of time your code spends communicating to the amount of time it spends computing. ...
doi:10.5120/ijca2016911273
fatcat:xkcr4hvdpnfcfarkea2y5cxdhu
Performance and Energy Analysis of the Iterative Solution of Sparse Linear Systems on Multicore and Manycore Architectures
[chapter]
2014
Lecture Notes in Computer Science
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High performance computing (HPC) initiatives
Not promote one particular hardware architecture
Simple implementation of CG
Standard sparse matrix-vector product codes
Use of standard numerical ...
library for the vector operations
Only apply compiler optimizations
Outline
Introduction
Solving Sparse SPD Linear Systems (CG)
Benchmark Matrices
Hardware Setup and Compilers
Experimental ...
and Manycore Architectures Thanks for your attention! ...
doi:10.1007/978-3-642-55224-3_72
fatcat:jtcxunch25csbfw45gpczhzpw4
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