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Optimizations for a simulator construction system supporting reusable components

David A. Penry, David I. August
2003 Proceedings of the 40th conference on Design automation - DAC '03  
With these optimizations, an LSE model using reusable components outperforms a SystemC model using custom components by 6%.  ...  While some systems support rapid model development through the structural composition of reusable concurrent components, the Liberty Simulation Environment (LSE) provides additional reuse-enhancing features  ...  ACKNOWLEDGEMENTS We would like to thank Manish Vachharajani, Neil Vachharajani, and the anonymous reviewers for their insightful comments.  ... 
doi:10.1145/776063.776065 fatcat:o64zorhp7nc7xh5hdgl4lvgmxm

Optimizations for a simulator construction system supporting reusable components

David A. Penry, David I. August
2003 Proceedings of the 40th conference on Design automation - DAC '03  
With these optimizations, an LSE model using reusable components outperforms a SystemC model using custom components by 6%.  ...  While some systems support rapid model development through the structural composition of reusable concurrent components, the Liberty Simulation Environment (LSE) provides additional reuse-enhancing features  ...  ACKNOWLEDGEMENTS We would like to thank Manish Vachharajani, Neil Vachharajani, and the anonymous reviewers for their insightful comments.  ... 
doi:10.1145/775832.776065 dblp:conf/dac/PenryA03 fatcat:nvo7nimafzhkbbvp2nb7rwo6he

Analysis of "SystemC" design flow for FPGA implementation

Kartika S
2016 International journal of new practices in management and engineering  
Using SystemC, Hardware IPs can be modeled at system level which helps to reduce the time to market for SOCs. In most applications SystemC is utilized to verify functionality of the design.  ...  The proposed method of synthesis would be time saving than the conventional design and synthesis using HDL in RTL perspective.  ...  FIR FILTER -Simulation Results.Fig 6: GCD -Simulation Results. The Verification of the SystemC code and design is done through Mentor graphics Questasim tool.  ... 
doi:10.17762/ijnpme.v5i01.41 fatcat:qmjupk5wrzafhncfuhgutew7fm

RTOS-aware refinement for TLM2.0-based HW/SW designs

Markus Becker, Giuseppe Di Guglielmo, Franco Fummi, Wolfgang Mueller, Graziano Pravadelli, Tao Xie
2010 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)  
This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device  ...  Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a tradeoff between timing accuracy of the used models and correct estimation of the final timing performance  ...  Since it is provided as a optimized SystemC library for fast simulation, we have selected it for our methodology.  ... 
doi:10.1109/date.2010.5456965 dblp:conf/date/BeckerGF0PX10 fatcat:h4sc5aol6rahxdz3e4ra5t6g7y

Fast Thermal Simulation using SystemC-AMS

Yukai Chen, Sara Vinco, Enrico Macii, Massimo Poncino
2016 Proceedings of the 26th edition on Great Lakes Symposium on VLSI - GLSVLSI '16  
These tools have many benefits, but they are relatively inefficient when performing thermal analysis for long simulation times, due to the occurrence of a large number of redundant computations intrinsic  ...  As a further advantage, the adoption of the same language to describe functionality and temperature allows the simultaneous simulation of both dimensions with no co-simulation overhead, thus enhancing  ...  The time is slightly higher for our approach, since it requires a further step to map the resistor and capacitor matrices to SystemC-AMS primitives, and to print the generated code onto a file.  ... 
doi:10.1145/2902961.2902975 dblp:conf/glvlsi/ChenVMP16 fatcat:2zn7xbgoqrcrvgblf6a737hy44

SystemC simulation on GP-GPUs

Nicola Bombieri, Sara Vinco, Valeria Bertacco, Debapriya Chatterjee
2012 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '12  
The generated simulator code targets both CUDA and OpenCL libraries, to boost scalability and provide support for multiple GP-GPU architectures.  ...  Parallelizing SystemC simulation entails a complete re-design of the simulator kernel for the specific target parallel architectures.  ...  SystemC simulation on CUDA GP-GPUs has been proposed for the first time in [13] .  ... 
doi:10.1145/2380445.2380500 dblp:conf/codes/BombieriVBC12 fatcat:2wjf7g2hj5da3cqt7kbv5m32my

Elaboration-time synthesis of high-level language constructs in SystemC-based microarchitectural simulators

Zhuo Ruan, Kurtis Cahill, David Penry
2010 2010 IEEE International Conference on Computer Design  
We propose an elaboration-time synthesis method for SystemCbased microarchitectural simulators.  ...  High-level language constructs such as templates and object polymorphism are used to achieve a high degree of code reuse, thereby reducing development time.  ...  We would also like to acknowledge Daniel Gracia Pérez, Giles Mouchard, and Olivier Temam for providing access to the Microlib DLX model.  ... 
doi:10.1109/iccd.2010.5647583 dblp:conf/iccd/RuanCP10 fatcat:dr63tde4ure2baxmrmesu63i4y

Towards an efficient assertion based verification of SystemC designs

A. Habibi, S. Tahar
2004 Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)  
Static code analysis will help generate a dependency relation between inputs and assertion parameters as well as define the ranges of inputs affecting the assertion, The genetic algorithm will optimize  ...  Experimental results illustrate the efficiency or our approach compared to random simulation.  ...  Events in SystemC occur at a given simulation time. PSL is an implementation independent language to define properties.  ... 
doi:10.1109/hldvt.2004.1431224 dblp:conf/hldvt/HabibiT04 fatcat:7bnsd4lcizfk5gbu3asieiaeta

Parallel simulation of mixed-abstraction SystemC models on GPUs and multicore CPUs

Rohit Sinha, Aayush Prakash, Hiren D. Patel
2012 17th Asia and South Pacific Design Automation Conference  
Hence, we co-simulate in parallel, the SystemC processes on multiple CPUs, and the GPU kernels on the GPUs; exploit both the CPUs, and GPUs for faster simulation.  ...  This work presents a methodology that parallelizes the simulation of mixed-abstraction level SystemC models across multicore CPUs, and graphics processing units (GPUs) for improved simulation performance  ...  [7] parallelize the simulation of SystemC RTL models on GPUs. They translate the SystemC model into CUDA code preserving the original DE semantics.  ... 
doi:10.1109/aspdac.2012.6164991 dblp:conf/aspdac/SinhaPP12 fatcat:2zhkm2yphvcfjf5gwhu64cpg2m

Using SystemC Cyber Models in an FMI Co-Simulation Environment: Results and Proposed FMI Enhancements

Stefano Centomo, Julien Deantoni, Robert de Simone
2016 2016 Euromicro Conference on Digital System Design (DSD)  
Both results are illustrated by using a simple but illustrative use case mixing models in SystemC (for the cyber part) and Modelica (for the physical part).  ...  In this context, this paper investigates how discreteevent models of the cyber part are supported by FMI standard for co-simulation.  ...  Finally, it continues the (co-)simulation for the required simulation time.  ... 
doi:10.1109/dsd.2016.86 dblp:conf/dsd/CentomoDS16 fatcat:cjo6h2djenfyfcfgfzlxcddx3y

A Smooth Refinement Flow for Co-designing HW and SW Threads

Paolo Destro, Franco Fummi, Graziano Pravadelli
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
However, Sys-temC threads, corresponding to the SW application, are simulated outside the control of the SystemC simulation kernel to exploit the typical features of multi-threading real-time operating  ...  On the contrary HW threads maintain the original simulation semantics of SystemC.  ...  of the coding effort, but also for the simulation of the design under refinement.  ... 
doi:10.1109/date.2007.364575 dblp:conf/date/DestroFP07 fatcat:geipe6u43fgujfwpcaa3mfhaxi

Native Binary Mutation Analysis for Embedded Software and Virtual Prototypes in SystemC

Christoph Kuznik, Wolfgang Muller
2011 2011 IEEE 17th Pacific Rim International Symposium on Dependable Computing  
In this paper we propose a mutation testing verification flow for SystemC based virtual prototypes that may not rely on source code only but on annotated basic blocks and enables mutant creation at assembler  ...  Here the industry is modeling both hardware and related software parts at higher levels of abstraction, called virtual prototypes, to accelerate parallel development and shorten time-to-market.  ...  This compiler-integrated technique for run-time optimization does not require the mutant to be compiled but to just patched in the original compilation based on the CFG analysis, reducing computational  ... 
doi:10.1109/prdc.2011.47 dblp:conf/prdc/KuznikM11 fatcat:6gqudckr2jfkplo3stbqariqxe

The Integration of SystemC and Hardware-Assisted Verification [chapter]

Ramaswamy Ramaswamy, Russell Tessier
2002 Lecture Notes in Computer Science  
Our interface methodology is demonstrated through the integration of a communication system design, written in C and SystemC, with a multi-FPGA logic emulator from Ikos Systems.  ...  Although gate-level emulation takes longer compared to behavioral SystemC verification, accuracy for the cores is enhanced.  ...  This methodology allows for the optimization of the verification hardware interface to SystemC and similar system-design languages.  ... 
doi:10.1007/3-540-46117-5_103 fatcat:bbzmpnnpqrazzfg54iiow3ijnq

A UML-based Environment for System Design Space Exploration

Ludovic Apvrille, Waseem Muhammad, Rabea Ameur-Boulifa, Sophie Coudert, Renaud Pacalet
2006 2006 13th IEEE International Conference on Electronics, Circuits and Systems  
Transformation rules were defined for generating from UML models either a SystemC model or a formal specification given in LOTOS.  ...  Thus, relying on SystemC or LOTOS tools the profile allows fast simulation or formal verification techniques to be used over the UML modeling. A toolkit supporting this profile has been implemented.  ...  After the mapping step, code may be generated and simulated.  ... 
doi:10.1109/icecs.2006.379694 dblp:conf/icecsys/ApvrilleWACP06 fatcat:ogsfviqyxrftvf5b2ngc5wurmm

ESL design and HW/SW co-verification of high-end software defined radio platforms

A. C. H. Ng, J. W. Weijers, M. Glassee, T. Schuster, B. Bougard, L. Van der Perre
2007 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '07  
Incremental RTL verification based on co-simulation and co-emulation is also presented.  ...  This paper demonstrates an integrated ESL design flow built on advanced ESL tools to design SDR platforms for handhelds.  ...  AMBA System SystemC RTL Other system level components SystemC RTL Stimuli generation and evaluation SystemC SystemC CODES+ISSS'07, September 30-October 3, 2007, Salzburg, Austria.  ... 
doi:10.1145/1289816.1289864 dblp:conf/codes/NgWGSBP07 fatcat:i76lkw33anhcllhiq3vtlb2z3y
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