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Co-scheduling hardware and software pipelines

R. Govindarajan, E.R. Altman, G.R. Gao
Proceedings. Second International Symposium on High-Performance Computer Architecture  
In this paper w e propose CO-Scheduling, a framework f o r simultaneous design of hardware pipelines structures and software-pipelined schedules.  ...  T w o important components of t h e Co-Scheduling framework are: (1) An extension t o t h e analysis of hardware pipeline design t h a t m e e t s t h e needs of periodic (or software pipelined) schedules  ...  Conclusions In this paper we have proposed Co-Scheduling, a unified framework that performs the scheduling of hardware and software pipelines.  ... 
doi:10.1109/hpca.1996.501173 dblp:conf/hpca/GovindarajanAG96 fatcat:tlcrrk7zxbdvzkar6kilgs654u

CAD tool for hardware software co-synthesis of heterogeneous multiple processor embedded architectures

Gul Nawaz Khan, Usman Ahmed
2008 Design automation for embedded systems  
Pipeline stages are created during the allocation and scheduling process. The overhead of task scheduling on software-PEs is ignored.  ...  Bakshi and Gajski have presented a co-synthesis technique involving pipelining and scheduling of multiple PEs [16] .  ...  The authors would like to acknowledge the support from CMC in terms of co-design tools and prototyping systems.  ... 
doi:10.1007/s10617-008-9031-1 fatcat:mbtaod6bbnestfidh4g7n7536u

Hardware/Software Co-Design Manuscript received February 1, 1996; revised December 2, 1996. This work was supported in part by DARPA, under Contract DABT 63-95-C-0049, and in part by NSF CAREER Award MIP 95-01615. Publisher Item Identifier S 0018-9219(97)02017-3 [chapter]

GIOVANNI DE MICHELI, RAJESH K. GUPTA
2002 Readings in Hardware/Software Co-Design  
Hardware/software co-design means meeting system-level objectives by exploiting the synergism of hardware and software through their concurrent design.  ...  Hardware circuits are often described using modeling or programming languages, and they are validated and implemented by executing software programs, which are sometimes conceived for the specific hardware  ...  The co-design of deeply pipelined microprocessors can leverage the coupling between instruction scheduling and hardware organization.  ... 
doi:10.1016/b978-155860702-6/50005-3 fatcat:6uahvlb44vc6fjlkqaqhet3gfe

Hardware/software co-design

G. De Michell, R.K. Gupta
1997 Proceedings of the IEEE  
Hardware/software co-design means meeting system-level objectives by exploiting the synergism of hardware and software through their concurrent design.  ...  Hardware circuits are often described using modeling or programming languages, and they are validated and implemented by executing software programs, which are sometimes conceived for the specific hardware  ...  The co-design of deeply pipelined microprocessors can leverage the coupling between instruction scheduling and hardware organization.  ... 
doi:10.1109/5.558708 fatcat:vyrbdbynszel3ku424iqlkh3sm

Hardware/Software Codesign [chapter]

2008 System-on-Chip Design and Technologies  
Hardware/software co-design means meeting system-level objectives by exploiting the synergism of hardware and software through their concurrent design.  ...  Hardware circuits are often described using modeling or programming languages, and they are validated and implemented by executing software programs, which are sometimes conceived for the specific hardware  ...  The co-design of deeply pipelined microprocessors can leverage the coupling between instruction scheduling and hardware organization.  ... 
doi:10.1201/9781420051735.ch3 fatcat:vzpfaqbtozbonfdgewlalozmya

Hardware-software Codesign

1997 IEEE Design & Test of Computers  
Hardware/software co-design means meeting system-level objectives by exploiting the synergism of hardware and software through their concurrent design.  ...  Hardware circuits are often described using modeling or programming languages, and they are validated and implemented by executing software programs, which are sometimes conceived for the specific hardware  ...  The co-design of deeply pipelined microprocessors can leverage the coupling between instruction scheduling and hardware organization.  ... 
doi:10.1109/mdt.1997.573370 fatcat:e3chtb5h6ffpphp3ixtkspfm4y

Hardware-software codesign

P. Gupta
2002 IEEE potentials  
Hardware/software co-design means meeting system-level objectives by exploiting the synergism of hardware and software through their concurrent design.  ...  Hardware circuits are often described using modeling or programming languages, and they are validated and implemented by executing software programs, which are sometimes conceived for the specific hardware  ...  The co-design of deeply pipelined microprocessors can leverage the coupling between instruction scheduling and hardware organization.  ... 
doi:10.1109/45.983337 fatcat:qi4ochkozrfbrgml7azzlxro7e

Pipelined Scheduling of Functional HW/SW Modules for Platform-Based SoC Design

Wonjong Kim, June-Young Chang, Hanjin Cho
2005 ETRI Journal  
We developed a pipelined scheduling technique of functional hardware and software modules for platformbased system-on-a-chip (SoC) designs. It is based on a modified list scheduling algorithm.  ...  We used the pipelined scheduling technique for a performance analysis of an MPEG4 video encoder application. Then, we applied it for architecture exploration to achieve a better performance.  ...  In this paper, we developed a pipelined scheduling technique of hardware and software modules for platform-based SoC design.  ... 
doi:10.4218/etrij.05.0905.0011 fatcat:5vuh2zd2rzejpmiaak3qjd3qdi

Transactors for parallel hardware and software co-design

Krste Asanovic
2007 2007 IEEE International High Level Design Validation and Test Workshop  
Introduction Complex, high-performance, low-power information processing systems usually incorporate a mixture of hardware and software elements, and pose significant design challenges.  ...  The execution datapath can be pipelined, and a single transaction might require several passes through the pipeline.  ... 
doi:10.1109/hldvt.2007.4392802 dblp:conf/hldvt/Asanovic07 fatcat:4kjzqrlhwnc4rdr2ws2dx7v2ay

A software-hardware cosynthesis approach to digital system simulation

K.A. Olukotun, R. Helaihel, J. Levitt, R. Ramirez
1994 IEEE Micro  
The components of the simulation compiler are a high performance compiled-code software simulator, an automatic partitioner that partitions the system model between the processor and FPGA, and a scheduler  ...  This paper presents a software-hardware based simulation approach to digital system simulation.  ...  that are possible using software-hardware co-synthesis.  ... 
doi:10.1109/40.296157 fatcat:xnex5qaserfsxigjvh2vyjguue

Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip

Yoon Seok Yang, Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh
2009 2009 Sixth International Conference on Information Technology: New Generations  
We show that our method has the advantage of flexibility as compared to previous implementations of cryptographic algorithms based on hardware and software co-design or traditional hardwired ASIC design  ...  In addition, the simulation result presents that the parallel and pipeline processing approach for software block ciphers can be implemented on various NoC platforms which have different complexities and  ...  Other researchers have proposed specialized instruction set architectures to accelerate cipher algorithms on hardware and software co-design platforms [9] , [7] , [13] .  ... 
doi:10.1109/itng.2009.163 dblp:conf/itng/YangBLB09 fatcat:zma47ueo5zex3gatzixeo4k5im

Hardware-software architecture for priority queue management in real-time and embedded systems

N.G. Chetan Kumar, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones
2014 International Journal of Embedded Systems  
His research interests include embedded and real-time systems and hardware/software co-design.  ...  We assert a hardware-software co-design approach is required to elegantly overcome these limitations.  ...  Acknowledgements This work is supported in part by the National Science Foundation (NSF) under award CNS-1060337, and by the Air Force Office of Scientific Research (AFOSR) under award FA9550-11-1-0343  ... 
doi:10.1504/ijes.2014.064997 fatcat:kcjjjkcyhffmddtazwsry3z4ri

Cycle and phase accurate DSP modeling and integration for HW/SW co-verification

Lisa Guerra, Joachim Fitzner, Dipankar Talukdar, Chris Schläger, Bassam Tabbara, Vojin Zivojnovic
1999 Proceedings of the 36th ACM/IEEE conference on Design automation conference - DAC '99  
We present our practical experience in the modeling and integration of cycle/phase-accurate instruction set architecture (ISA) models of digital signal processors (DSPs) with other hardware and software  ...  The additional extensive modeling of the pipeline and other architectural details in the BIM would force us to develop two detailed processor models with a complex BIM API between them.  ...  The latter collects the information about the software events, identifies the corresponding hardware events, and schedules them in proper order for each clock cycle.  ... 
doi:10.1145/309847.310107 dblp:conf/dac/GuerraFTSTZ99 fatcat:fip2bybtznftvctrvgbhaymtne

Hardware/software co-compilation with the Nymble system

Jens Huthmann, Bjorn Liebig, Julian Oppermann, Andreas Koch
2013 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)  
The system also supports calls from hardware back into software, both for infrequent operations that do not merit hardware area, as well as for using operating system / library services such as memory  ...  The interface logic between the remaining software parts and the accelerators is automatically created, taking into account details such as cache flushes and copying of FPGA-local memories to the shared  ...  Hardware/Software Co-Execution Model Nymble's hardware/software co-execution model requires a tight coupling between SPP and RCU.  ... 
doi:10.1109/recosoc.2013.6581538 dblp:conf/recosoc/HuthmannLO013 fatcat:akq34rxu35au3hto5whi5m4ryu

Characterising radio telescope software with the Workload Characterisation Framework [article]

Y.G. Grange, R. Lakhoo, M. Petschow, C. Wu, B. Veenboer, I. Emsley, T.J. Dijkema, A. P. Mechev, G. Mariani
2016 arXiv   pre-print
As a demonstration, we discuss the experiences using the framework to characterise a LOFAR calibration and imaging pipeline.  ...  We present a modular framework, the Workload Characterisation Framework (WCF), that is developed to reproducibly obtain, store and compare key characteristics of radio astronomy processing software.  ...  We thank Marco Iacobelli for providing the Calib processing pipeline and the input data.  ... 
arXiv:1612.00456v1 fatcat:5gj6b53av5fw7nzuihp6qmmn4i
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