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Co-Designed FreeRTOS Deployed on FPGA

Jorge Pereira, Daniel Oliveira, Sandro Pinto, Nuno Cardoso, Vitor Silva, Tiago Gomes, Jose Mendes, Paulo Cardoso
2014 2014 Brazilian Symposium on Computing Systems Engineering  
The developed hardware accelerators were synthesized on a field-programmable gate array (FPGA), exploiting the point-to-point bus Fast Simplex Link (FSL) to interconnect to the Xilinx's Microbaze soft-core  ...  Unfortunately, this new layer on an embedded system puts more pressure on the aforementioned metrics.  ...  in Xilinx FPGAs [13] .  ... 
doi:10.1109/sbesc.2014.11 dblp:conf/sbesc/PereiraOPCSGMC14 fatcat:exemmbvnkzcm5heonxwg4hidyy

Virtualized Execution Runtime for FPGA Accelerators in the Cloud

Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne
2017 IEEE Access  
In order to start the FPGA application, the user thread on the host CPU passes the package to the manager thread, which deploys it to the FPGA.  ...  Outl can benefit from an underutilized FPGA by deploying multiple instances of the same accelerator on as many locations as the runtime manager can provide.  ... 
doi:10.1109/access.2017.2661582 fatcat:donw4yrggjdftkgob3x5l5r664

Real-Time Operating System FreeRTOS Application for Fire Alarm Project in Reduced Scale

Luca de Oliveira Turci
2017 International Journal of Computing and Digital Systems  
Hence, the design of a system in order to reduce such problems may be considered relevant.  ...  In the proposed project, an algorithm was developed by using Arduino Nano and FreeRTOS open source kernel in order to accomplish such task in a reduced scale project.  ...  The Arduino Nano is based on the ATmega328 and it is compatible with the FreeRTOS platform. D.  ... 
doi:10.12785/ijcds/060405 fatcat:ylnxaeol2bfo3jfck26ypcveqy

Adaptive Fuzzy Hardware Scheduler for Real Time Operating System

D. G. Harkut, et.al.
2016 International Journal of Computing and Digital Systems  
Scheduling algorithms play an important role in the design of real-time systems.  ...  The increased computation overheads resulted from proposed model can be compensated by exploiting the parallelism of the hardware as being migrated to FPGA.  ...  [37] come up with H-Kernel, an outcome of through use of FPGA and thoughtful HW/SW co-design for specific application.  ... 
doi:10.12785/ijcds/050606 fatcat:2vlhjuiqgnbrrdo42gqsk3gw34

Co-Design of Multicore Hardware and Multithreaded Software for Thread Performance Assessment on an FPGA

George K. Adam
2022 Computers  
level parallelism (TLP) of tasks running in parallel as threads on multiple cores.  ...  The results reveal that parallel implementation of the prevalent merge sort and quicksort algorithms on this platform is more efficient.  ...  Design Methodology The co-design of the proposed system encompassed hardware and software parts.  ... 
doi:10.3390/computers11050076 fatcat:kyuy3opsg5h2fputitwzedltim

Analysis of the Usage Models of System Memory Management Unit in Accelerator-attached Translation Units

Kyriakos Paraskevas, Konstantinos Iordanou, Mikel Luján, John Goodacre
2020 The International Symposium on Memory Systems  
We analyze the generic structure on SoCs given the example of the Zynq Ultrascale+ FPGA board that incorporates the state-of-the-art and widely used Arm System Memory Management Unit.  ...  In accelerator-enabled environments, accelerator units are able to deliver a substantial increase in performance through increased programming effort and co-scheduling applications across the heterogeneous  ...  The FPGA hardware design The testbench hardware design deployed on FPGA was implemented in Vivado [37] , a software suite by Xilinx for synthesis and analysis of Hardware Description Language (HDL) designs  ... 
doi:10.1145/3422575.3422781 fatcat:2iiamumcjfenjnbe4de7ts3fh4

FPGA based Real Time simulations of the face milling process

Michal R. Mazur, Marek A. Galewski, Krzysztof J. Kalinski
2020 IEEE Access  
the Polish National Center for Research and Development, project TANGO1 / 266350 / NCBR / 2015 "Application of selected mechatronic solutions to supervise the cutting process of large-size workpieces on  ...  However, SDSoC automates the integration of hardware-implemented functions (Vivado's block design process) and provides drivers and runtimes for various runtime environments: Linux, FreeRTOS, and Baremetal  ...  For standalone units, it may be required to implement all additional components in the hardware (e.g., a serial port used for communication between FPGA and PC) or to deploy some FPGA resources for a programmable  ... 
doi:10.1109/access.2020.3041177 fatcat:rby5jevgw5eghgqgawnk4ytrbe

Fault-Tolerant FPGA-Based Nanosatellite Balancing High-Performance and Safety for Cryptography Application

Laurent Gantel, Quentin Berthet, Emna Amri, Alexandre Karlov, Andres Upegui
2021 Electronics  
With the growth of the nano-satellites market, the usage of commercial off-the-shelf FPGAs for payload applications is also increasing.  ...  The relevance of the platform is demonstrated in a nano-satellite cryptographic application running on a Zynq UltraScale+ MPSoC device.  ...  On the Cortex-A53, the first core hosts the payload application which runs on top of a FreeRTOS operating system [15] .  ... 
doi:10.3390/electronics10172148 doaj:20c47a53a273458ab46b8f6ad6c11937 fatcat:vlj2murgcfdupn3gitld635wwi

TyTAN

Ferdinand Brasser, Brahim El Mahjoub, Ahmad-Reza Sadeghi, Christian Wachsmann, Patrick Koeberl
2015 Proceedings of the 52nd Annual Design Automation Conference on - DAC '15  
We implemented TyTAN on the Intel Siskiyou Peak embedded platform and demonstrate its efficiency and effectiveness through extensive evaluation.  ...  This work has been co-funded by the German Science Foundation as part of  ...  We implemented TyTAN on a Xilinx Spartan-6 FPGA running at 48 MHz. Operating System. TyTAN uses the FreeRTOS 4 real-time operating system.  ... 
doi:10.1145/2744769.2744922 dblp:conf/dac/BrasserMSWK15 fatcat:jwwzz2teonamli7gwgbc2vy6rq

Real-time capable hardware-based parser for efficient XML interchange

Vlado Altmann, Jan Skodzik, Peter Danielis, Nam Pham Van, Frank Golatowski, Dirk Timmermann
2014 2014 9th International Symposium on Communication Systems, Networks & Digital Sign (CSNDSP)  
ACKNOWLEDGMENT We would like to thank the German Federal Institute for Research on Building, Urban Affairs and Spatial Development (BBSR) within the Federal Office for Building and Regional Planning for  ...  Despite slightly higher resource consumption, the co-design still fits into the FPGA.  ...  Moreover, the AXI interface requires additional FPGA resources, which are for the co-design 12999 registers (12 % of total amount) and 17868 lookup tables (33 % of total amount).  ... 
doi:10.1109/csndsp.2014.6923861 dblp:conf/csndsp/AltmannSDVGT14 fatcat:kbzw6luqynaghjvydd227rhzdm

A Bandwidth Reservation Mechanism for AXI-Based Hardware Accelerators on FPGAs

Marco Pagani, Enrico Rossi, Alessandro Biondi, Mauro Marinoni, Giuseppe Lipari, Giorgio Buttazzo, Michael Wagner
2019 Euromicro Conference on Real-Time Systems  
silicon or dynamically deployed on FPGA fabric.  ...  on FPGAs.  ...  Figure 1 1 Figure 1 Block diagram of a custom system deployed on a SoC-FPGA platform.  ... 
doi:10.4230/lipics.ecrts.2019.24 dblp:conf/ecrts/PaganiRBMLB19 fatcat:tuyxzsa4hnc4zhmddo3ppns6ka

Pushing the Level of Abstraction of Digital System Design: a Survey on How to Program FPGAs

Emanuele Del Sozzo, Davide Conficconi, Alberto Zeni, Mirko Salaris, Donatella Sciuto, Marco D. Santambrogio
2022 ACM Computing Surveys  
However, FPGA adoption found limitations in their programmability and required knowledge. Therefore, researchers focused on FPGA abstractions and automation tools.  ...  Here, we survey three leading digital design abstractions: Hardware Description Languages (HDLs), High-Level Synthesis (HLS) tools, and Domain-Specific Languages (DSLs).  ...  On the one hand, it automatically implements the hardware functions on FPGA, and, on the other hand, it generates the host code for bare metal, Linux, or FreeRTOS.  ... 
doi:10.1145/3532989 fatcat:nsk5lwvt3vba5fbxmaj7sgpwru

Model-based Approach for Automatic Generation of Hardware Architectures for Robotics

Ariel Podlubne, Johannes Mey, Rene Schone, Uwe Abmann, Diana Gohringer
2021 IEEE Access  
The second one consists of a fully FPGA-based mobile platform with ROS features incorporated.  ...  FPGAs are ideal candidates to enhance those systems computing capabilities while still being programmable.  ...  Besides, it helps non-experts to focus only on their areas of expertise (e.g., HW/SW Co-design, algorithms, control).  ... 
doi:10.1109/access.2021.3119061 fatcat:2tdl3xurg5aitnrp4xy5tamrte

Control and Visualisation of a Software Defined Radio System on the Xilinx RFSoC Platform Using the PYNQ Framework

Joshua Goldsmith, Craig Ramsay, David Northcote, Kenneth W. Barlee, Louise H. Crockett, Robert W. Stewart
2020 IEEE Access  
In doing so, we highlight features that can be extremely useful for prototyping radio system design.  ...  The availability of commercial Radio Frequency System on Chip (RFSoC) devices brings new possibilities for implementing Software Defined Radio (SDR) systems.  ...  Also, the control aspects provide a good basis for an interactive dashboard in a deployed design.  ... 
doi:10.1109/access.2020.3008954 fatcat:523zk3j6fva5bbb2rwmcawqnea

Inception: System-Wide Security Testing of Real-World Embedded Systems Software

Nassim Corteggiani, Giovanni Camurati, Aurélien Francillon
2018 USENIX Security Symposium  
Connected embedded systems are becoming widely deployed, and their security is a serious concern.  ...  Current techniques for security testing of embedded software rely either on source code or on binaries.  ...  Inspired by SURROGATES [17] , we designed a custom device based on a Xilinx ZedBoard FPGA [11] , to efficiently translate high-level read/write commands into low-level JTAG signals. 8 The FPGA is connected  ... 
dblp:conf/uss/CorteggianiCF18 fatcat:2ehpqxiidjedvpjqmyfrmf37eq
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