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Clock period minimization of semi-synchronous circuits by gate-level delay insertion

T. Yoda, A. Takahashi, Y. Kajitani
1999 Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)  
We show that this bound is achieved in the semi-synchronous framework by the proposed gate-level delay insertion method on the assumption that the delay of each element on the circuit is unique.  ...  A feature of semi-synchronous circuits is that the minimum delay between registers may be critical with respect to the clock period of the circuit.  ...  Here, the number of gates is denoted by Gate, the maximum delay-to-register ratio is denoted by MD, the clock period of the semi-synchronous circuit before delay insertion is denoted by Initial, the clock  ... 
doi:10.1109/aspdac.1999.759775 dblp:conf/aspdac/YodaTK99 fatcat:p7gbievxnrfhlcpippqz4xn4sa

A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework

Y. KOHIRA, A. TAKAHASHI
2008 IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences  
In this paper, we propose a gate-level register relocation method that reduces the number of registers while keeping the target clock period.  ...  Under the assumption that the clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period might be reduced by register relocation while maintaining the circuit behavior  ...  Acknowledgments This research was partially supported by Japan Society for the Promotion of Science (JSPS), Research Fellow-ship for Young Scientist 19-6015, 2007.  ... 
doi:10.1093/ietfec/e91-a.10.3030 fatcat:pebn7kztdnc5zg5i5zwlk6xp6m

Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization

Y. KOHIRA, A. TAKAHASHI
2007 IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences  
We prove that the proposed method achieves the clock period achieved by retiming with delay decomposition, if the delay of each element in the circuit is unique.  ...  In this paper, we propose a gate-level register relocation method to reduce the minimum feasible clock period. The proposed method is a greedy local circuit modification method.  ...  In this paper, we propose a gate-level register relocation method in g-frame for the clock period minimization.  ... 
doi:10.1093/ietfec/e90-a.4.800 fatcat:3bzle6tev5hvvc7vmhk443zrfu

Design Automation of Real-Life Asynchronous Devices and Systems

Alexander Taubin, Jordi Cortadella, Luciano Lavagno, Alex Kondratyev, Ad Peeters
2006 Foundations and Trends® in Electronic Design Automation  
Designers of such circuits consider fanout in critical wires to be safe by assuming that the skew between wire branches is less than the minimum gate delay.  ...  Gate-level pipelining [117, 118] , on the other hand, can pipeline at the level of individual gates, thus achieving performance levels that are virtually impossible to match with synchronous designs.  ... 
doi:10.1561/1000000006 fatcat:5cfzhblspza53gfakyfcine2m4

Modeling and design of asynchronous circuits

M.B. Josephs, S.M. Nowick, C.H. Van Berkel
1999 Proceedings of the IEEE  
There are seven main points. 1) Signal transitions provide a key to understanding the switching behavior of asynchronous logic. 2) Burst-mode circuits and speed-independent control circuits offer reliable  ...  operation that is free from glitches. 3) Various notations are available for specification of control circuitry and as a starting point for logic synthesis. 4) Bundled data and delay-insensitive coding  ...  at the beginning and end of each clock period.  ... 
doi:10.1109/5.740017 fatcat:ud3rqhiozja6rkf5prhsnvr35q

Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications

J. Cortadella, A. Kondratyev, L. Lavagno, C.P. Sotiriou
2006 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
delays at design time and constrain the clock cycle accordingly.  ...  Desynchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus, permitting widespread adoption of asynchronicity without requiring special design  ...  This shows that the behavior of a desynchronized circuit has a well-defined periodicity, similar to that of a synchronous one, paced by a common clock.  ... 
doi:10.1109/tcad.2005.860958 fatcat:tgpvvx2cqncezougkjl67ymese

Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks [chapter]

Konrad Kulikowski, Alexander Smirnov, Alexander Taubin
2006 Lecture Notes in Computer Science  
It allows synthesis of asynchronous quasi delay insensitive circuits from standard high-level hardware description language (HDL) specifications.  ...  Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks.  ...  Acknowledgements This work was partially funded by Omnibase Logic Inc.  ... 
doi:10.1007/11894063_31 fatcat:v7mshto3evbfrc55vgumhsqvvu

VeriSFQ - A Semi-formal Verification Framework and Benchmark for Single Flux Quantum Technology [article]

Alvin D. Wong, Kevin Su, Hang Sun, Arash Fayyazi, Massoud Pedram, and Shahin Nazarian
2019 arXiv   pre-print
The VeriSFQ framework focuses on verifying the key circuit and gate-level properties of SFQ logic: fanout, gate-level pipeline, path balancing, and input-to-output latency.  ...  gates.  ...  The research is based upon work supported by the Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA), via the U.S.  ... 
arXiv:1903.07025v1 fatcat:fzicutxsprfidchettmpmvkk4a

Asynchronous Design—Part 2: Systems and Methodologies

Steven M. Nowick, Montek Singh
2015 IEEE design & test  
Part 2 focuses on methodologies for designing asynchronous systems, including basics of hazards, synthesis and optimization methods for both logic-level and high-level synthesis, and the development of  ...  h THIS TWO-PART article aims to provide both a short historical and technical overview of asynchronous design, as well as a snapshot of the state of the art.  ...  Acknowledgment The authors appreciate the funding support of the National Science Foundation under Grants CCF-1219013, CCF-0964606, and OCI-1127361.  ... 
doi:10.1109/mdat.2015.2413757 fatcat:bpxnljdkofh6ppyovk6sp4pknm

Developing mesochronous synchronizers to enable 3D NoCs

Igor Loi, Federico Angiolini, Luca Benini
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
One of the foremost is the unsuitability of a purely synchronous design style, as it is not straightforward to impose a strict bound on the clock skew among multiple clock trees across different layers  ...  The next challenge is to use NoCs as the backbones of the upcoming generation of 3D chips, assembled by stacking multiple silicon layers. Multiple technical issues have to be tackled in this respect.  ...  Acknowledgments This work is supported by a grant from Semiconductor Research Corporation (SRC project number 1188) and a grant by STMicroelectronics for DEIS.  ... 
doi:10.1145/1403375.1403717 fatcat:62onfdatcfbtpa77kytqfb2qve

GaAs integrated circuits for error-rate measurement in high-speed digital transmission systems

C.A. Liechti, R. Joly, M. Namjoo
1983 IEEE Journal of Solid-State Circuits  
In order to operate this circuit at its highest speed, it is important to minimize the propagation delay in the feedback through the Exchrsive-oR gate.  ...  The clock CK* for this register is delayed with respect to the main clock, CK, to compensate for the signal delay in the Exchrsive-oR gates.  ...  Currentlv. he is employed at the Computer Research Center of Hewlett-Packard Laboratories working in the area of VLSI processors.  ... 
doi:10.1109/jssc.1983.1051963 fatcat:rcbrg4l765hoporuhwvrre6utq

Enhancing the Tolerance to Power-Supply Instability in Digital Circuits

J. Semiao, J. Freijedo, J.J. Rodriguez Andina, F. Vargas, M. B. Santos, I. C. Teixeira, J. P. Teixeira
2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)  
Moreover, when clock frequency reduction is inevitable, circuit tolerance when disturbances start to occur is enhanced, allowing the clock generator to react and reduce its frequency.  ...  The underlying idea is to add additional tolerance to the edge trigger of the clock signal driving specific memory cells. The clock duty-cycle (CDC) is thus dynamically modulated according to V DD .  ...  The clock period is t CLK = 1 GHz. The inverter chain is terminated by a level-sensitive D-type flip-flop (D-FF).  ... 
doi:10.1109/isvlsi.2007.44 dblp:conf/isvlsi/SemiaoFRVSTT07 fatcat:slhlggdxwrfhlfwvyzx6bsxtme

Elasticity and Petri Nets [chapter]

Jordi Cortadella, Michael Kishinevsky, Dmitry Bufistov, Josep Carmona, Jorge Júlvez
2008 Lecture Notes in Computer Science  
Time elastic systems can be constructed either by replacing the clock with communication handshakes (asynchronous version) or by augmenting the clock with a synchronous version of a handshake (synchronous  ...  Time elastic systems can tolerate static and dynamic changes in delays (asynchronous case) or latencies (synchronous case) of operations that can be used for modularity, ease of reuse and better power-delay  ...  As in regular synchronous circuits, signals must stabilize only by the end of the clock period and are allowed to have glitches.  ... 
doi:10.1007/978-3-540-89287-8_13 fatcat:72dwdfeh4vbmtdz3tp5jdraaj4

Power minimization in IC design: principles and applications

Massoud Pedram
1996 ACM Transactions on Design Automation of Electronic Systems  
, and physical levels of design abstraction.  ...  This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logical  ...  Additionally, by inserting variable-delay buffers in a circuit, the delays of all paths in the circuit can be made equal.  ... 
doi:10.1145/225871.225877 fatcat:jv72d4vvgfcmhmsmfazpkooyge

Soft MOUSETRAP: A Bundled-Data Asynchronous Pipeline Scheme Tolerant to Random Variations at Ultra-Low Supply Voltages

Jian Liu, Steven M. Nowick, Mingoo Seok
2013 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems  
Asynchronous circuits have no centralized or global clock.  ...  asynchronous designs can have significantly lower area than synchronous designs, and can provide much lower average power even than synchronous clock-gated designs.  ...  This research aims instead to provide a system controlled not by the clock, but by the actual arrival of each event.  ... 
doi:10.1109/async.2013.29 dblp:conf/async/LiuNS13 fatcat:pgi4on5mbffj3fylrygmhghspy
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