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Clock Distribution Strategy for IP-based Development [chapter]

Rui L. Aguiar, Dinis M. Santos
2000 IFIP Advances in Information and Communication Technology  
This paper presents a high-level clock distribution strategy for usage in a design-and-reuse environment.  ...  A new clock frequency multiplication structure optimised for this clock distribution strategy is finally proposed, since multifrequency clock support is highly desired.  ...  Clock Feedback Design Philosophy Clock distribution across several IP-based blocks should minimize both skew and jitter, as no information on the content of each block may be available.  ... 
doi:10.1007/978-0-387-35498-9_17 fatcat:u6zxh24hanaiva2dz6xkzerd2a

Low Power System-on-Chip Platform Architecture for High Performance Applications [chapter]

W.-C. Lo, A. T. Erdogan, T. Arslan
2003 The Kluwer International Series in Engineering and Computer Science  
This paper describes work on the development of a scheme for implementation of low power high performance Digital Signal Processing intensive AMBA based System-On-Chip platforms.  ...  The scheme is based on a novel interfacing scheme which utilises the bus hierarchy within AMBA in order to allow single and multiple high performance DSP Intellectual Property cores to be integrated into  ...  An AMBA-based low power clocking scheme is devised for the interface to reduce the switching activity in the AMBA interface and the connecting DSP IP Cores.  ... 
doi:10.1007/978-1-4615-0351-4_32 fatcat:4v5qfbbsundi5hcke7qmvxzjg4

Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques

Julian Pontes, Matheus Moreira, Rafael Soares, Ney Calazans
2008 2008 IEEE Computer Society Annual Symposium on VLSI  
The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC).  ...  This happens because of several factors: (i) constraining all modules to work at a single clock frequency leads to suboptimal designs; (ii) the clock distribution is responsible for a significant part  ...  IP Core reuse is indicated as one of the main techniques to reduce SoC development time [3] .  ... 
doi:10.1109/isvlsi.2008.90 dblp:conf/isvlsi/PontesMSC08 fatcat:ckurosr3x5bwvh5jyystmyypxy

Flexibly Mapping Synchronous Groupware Architectures to Distributed Implementations [chapter]

Tore Urnes, T. C. Nicholas Graham
1999 Eurographics  
Design-level architectures allow developers to concentrate on the functionality of their groupware application without exposing its detailed implementation as a distributed system.  ...  Because they abstract issues of distribution, networking and concurrency control, design-level architectures can be implemented using a range of distributed implementation architectures.  ...  Thanks also to Saul Greenberg and Mark Roseman for permitting us to use the GroupKit session manager [21] .  ... 
doi:10.1007/978-3-7091-6815-8_10 fatcat:k4hhs2rtkrdsjazwnstw5k4hj4

Configurable SID-based multi-core simulators for embedded system education

Chung-Wen Huang, Wei-Kuan Shih, Yarsun Hsu, Jenq Kuen Lee
2009 Proceedings of the 2009 Workshop on Embedded Systems Education - WESS '09  
SID Framework for Embedded System Course • The tool is developed to hope to be able to provide labs for several graduate embedded courses. • Strategies: Snapshots of execution Embedded • Trace the accessing  ...  We developed an embedded multi-core platform based on SID framework. • It included MPU, DSP, interconnection, and trace unit. . • It accommodated ingenious local IPs such as MPU and DSP. • It's useful  ... 
doi:10.1145/1719010.1719021 fatcat:ebo4ymvqdbbknj7klhakohhwye

'CLOCK SPEED' THEORY OF STRATEGY MAKING ALONG THE LIFE CYCLE

Tomas Koplyay, Hilda Hurta
2016 Polish Journal of Management Studies  
This article will present a model that can be relied upon to gauge the need for different strategic engagements at four critical points of the market development: start-up, growth, leveling off/shakeout  ...  Regardless of sector, the long term viability of a firm is strongly tied to the quality and timeliness of its strategies.  ...  The developing ties also slow down the clock speed as decisions need to be cycled among partners for approvals (Koplyay et al., 2011a) .  ... 
doi:10.17512/pjms.2016.13.1.10 fatcat:rxdxegqjlfg7vbd4ppm7u45lxe

Trends in Basic Sciences Education in Dental Schools, 1999-2016

Marilyn Lantz
2017 Journal of Dental Education  
Great variability was noted in the total clock hours of instruction and the clock hours of basic sciences instruction reported by dental schools.  ...  Overall, trends in the basic sciences curriculum in medical education were similar to those for dental education.  ...  represented on average 16-18% of the total clock hours of instruction between 1999 and 2011. 4-8 The average distribution of basic sciences clock hours between didactic and laboratory instruction remained  ... 
doi:10.21815/jde.017.008 pmid:28765456 fatcat:expuqgkusvebpjplu5bomrn6v4

A Power Consumption Estimation Approach for Embedded Software Design Using Trace Analysis

Yassine Ben Atitallah, Julien Mottin, Nicolas Hili, Thomas Ducroux, Guillaume Godet-Bar
2015 2015 41st Euromicro Conference on Software Engineering and Advanced Applications  
In this paper, we propose a lightweight and cost-effective approach suitable for software developers.  ...  With the explosion of advanced power control knobs such as dynamic voltage frequency scaling, mastering energy constraints in embedded systems is becoming challenging for software developers.  ...  It is based on an extension of the IP-XACT standard that captures power information and can be served as a unique, complete and comprehensive documentation for the SW developer. III.  ... 
doi:10.1109/seaa.2015.34 dblp:conf/euromicro/AtitallahMHDG15 fatcat:jztvi5kd6na2dojk47gicmx3ou

Network-on-Chip Firewall: Countering Defective and Malicious System-on-Chip Hardware [chapter]

Michael LeMay, Carl A. Gunter
2015 Lecture Notes in Computer Science  
Malicious IP or software could compromise critical data.  ...  They usually contain a System-on-Chip (SoC), which integrates microprocessors and peripheral Intellectual Property (IP) connected by a Network-on-Chip (NoC).  ...  We developed a simple network keylogger to be injected using the malicious IP.  ... 
doi:10.1007/978-3-319-23165-5_19 fatcat:ic23taltvnhmbasrdaicwcekuu

Design and Development of Comprehensive Railway Information and Communication Systems

Damir M. Zaborski, Zoran Ž Avramović
2018 JTTTP - JOURNAL OF TRAFFIC AND TRANSPORT THEORY AND PRACTICE  
Considering that the railway modernization represents an uninterrupted process, it is necessary to ensure constant technical and technological development and application of the latest achievements in  ...  Therefore, the role of the information and communication system (ICS) has irreplaceable importance for operation and functioning of the railways.  ...  INF3 interface with OA system IKS provides data communication channel for OA system, based on IP protocol. The connection is enabled using 10M/100M Ethernet port.  ... 
doi:10.7251/jtttp1801005z fatcat:tmqw22m4bbhdncmjvbcb6b6wty

Real-time operating environmentfor networked control systems

Won-jong Kim, Kun Ji, A. Ambike
2006 IEEE Transactions on Automation Science and Engineering  
This paper presents the development of a novel realtime operating environment for networked control systems (NCSs).  ...  A client-server architecture on a local-area network was developed with the network communication based on the user datagram protocol. The control loop of our NCS is closed over the network.  ...  Jayasuriya for their valuable comments and suggestions.  ... 
doi:10.1109/tase.2005.862146 fatcat:q5gd5vjcsvhxlhmt3hlnhor6yq

Watermarking Technique for HDL-based IP Module Protection

Min-Chuan Lin, Guo-Ruey Tsai, Chun-Rong Wu, Ching-Hui Lin
2007 Third International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2007)  
Without changing the original algorithm in the reused device and increasing extra HDL modules, the proposed watermarking technique is suitable for HDL-based reused IP protection.  ...  Reuse-based intellectual property (IP) design is one of the most promising techniques to take the SoC design quickly into market.  ...  How to protect the HDL_based IP is the key factor for prosperous marketing of soft IP. SoC design adopts reusable IP module to shorten development period and cut cost.  ... 
doi:10.1109/iih-msp.2007.326 dblp:conf/iih-msp/LinTWL07 fatcat:o6q2tbma5rdylbnqbrke6m7whu

Verification strategy for integration 3G baseband SoC

Yves Mathys, André Châtelain
2003 Proceedings of the 40th conference on Design automation - DAC '03  
We conclude with proposals and opportunities to enhance the SoC verification strategies based on the lessons learned.  ...  The verification strategy of the second generation Motorola triprocessors baseband chip for the 3G wireless phone market is presented.  ...  The current ECO technique based on spare cells is too limited, redundant hardware should be explored as the cost of the transistors is diminishing, especially for new IP on first Silicon.  ... 
doi:10.1145/775832.775835 dblp:conf/dac/MathysC03 fatcat:wviabrbrrrai7n6l7ymxmpar24

Verification strategy for integration 3G baseband SoC

Yves Mathys, André Châtelain
2003 Proceedings of the 40th conference on Design automation - DAC '03  
We conclude with proposals and opportunities to enhance the SoC verification strategies based on the lessons learned.  ...  The verification strategy of the second generation Motorola triprocessors baseband chip for the 3G wireless phone market is presented.  ...  The current ECO technique based on spare cells is too limited, redundant hardware should be explored as the cost of the transistors is diminishing, especially for new IP on first Silicon.  ... 
doi:10.1145/775833.775835 fatcat:drpwue65lrbbjbymod7rqpq4si

Effective Network Interface Architecture for Fault-Tolerant Mechanism Network-on-Chip

2019 VOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE  
In this paper an effective network interfaces architecture if introduced for fault tolerant mechanism network on chip.  ...  This system will exploit the speed of appropriate wire engineering which will transfer the long distance in single clock cycle.  ...  In bus-based communication, a shared communication bus is provided that connects multiple IP cores.  ... 
doi:10.35940/ijitee.l3949.1081219 fatcat:4iiwx365yzhbhfpujb5owdtkbm
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