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Clock construction in fully asynchronous parallel systems and PRAM simulation
1994
Theoretical Computer Science
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Aumann, Y. and M.O. Rabin, Clock construction in fully asynchronous parallel systems and PRAM simulation, Theoretical Computer Science 128 (1994) 3-30. ...
We provide detailed definitions of these asynchronous systems and their atomicity properties. The first construction in this paper is a novel clock for asynchronous systems. ...
We formally describe two such systems: the fully asynchronous parallel system (FAPS) and the atomic asynchronous parallel system (AAPS). ...
doi:10.1016/0304-3975(94)90162-7
fatcat:3givgzx7bzax7iho4e7ejccyjm
Page 1748 of Mathematical Reviews Vol. , Issue 95c
[page]
1995
Mathematical Reviews
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95c:68098 68Q22 68Q05
Aumann, Yonatan (1-MIT-C; Cambridge, MA);
Rabin, Michael O. (1-HRV-C; Cambridge, MA)
Clock construction in fully asynchronous parallel systems and PRAM simulation. ...
We provide detailed definitions of these asynchronous systems and their atomicity properties.
“The first construction in this paper is a novel clock for asyn- chronous systems. ...
A more practical PRAM model
1989
Proceedings of the first annual ACM symposium on Parallel algorithms and architectures - SPAA '89
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This paper introduces the Asynchronous PRAM model of computation, a variant of the PRAM in which the processors run asy ~chronously and there is an explicit charge for synchronization. ...
Algorithms, lower bounds, and simulation results are presented for an interesting member of the family. ...
Acknowledgement I thank Richard Karp, Jorge Sanz, Danny Soroker, and Edith Cohen for helpful discussions. ...
doi:10.1145/72935.72953
dblp:conf/spaa/Gibbons89
fatcat:mqwwiodoxvemtpenn4dhvstzdi
A PRAM-NUMA model of computation for addressing low-TLP workloads
2010
2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)
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and hashing to avoid hot spots in intercommunication. ...
In this paper we show that integrating non-uniform memory access (NUMA) support to the PRAM implementation architecture can solve this problem and provide a natural way for migration of the legacy code ...
Finally, it allows one to apply parallel programming techniques from fully asynchronous coarse grained threads (processors in the PRAM-NUMA model terminology) down to synchronous threads interchanging ...
doi:10.1109/ipdpsw.2010.5470846
dblp:conf/ipps/Forsell10
fatcat:52xppk5frzbbdh7kwrcspknlrq
Flexible Scheduling and Thread Allocation for Synchronous Parallel Tasks
2012
PARS Parallel-Algorithmen -Rechnerstrukturen und -Systemsoftware
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By aprototype implementation of asynchronous parallel task API in the SPMDbased PRAM language Fork and experimental evaluation with example programs on the SBPRAM simulator,w es howt hat ar ealization ...
uniform, unit-time memory access and strict memory consistency, also known in the literature as PRAMs (Parallel Random Access Machines). ...
Acknowledgments This research is funded by VTT,project REPLICA, and by SeRC. We thank the anonymous reviewers for their helpful comments. ...
doi:10.1007/bf03342029
fatcat:m26uvexwvvfnvibkgdg4tbeere
A PRAM-NUMA Model of Computation for Addressing Low-TLP Workloads
2011
International Journal of Networking and Computing
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and hashing to avoid hot spots in intercommunication. ...
In this paper we show that integrating non-uniform memory access (NUMA) support to the PRAM implementation architecture can solve this problem and provide a natural way for migration of the legacy code ...
Finally, it allows one to apply parallel programming techniques from fully asynchronous coarse grained threads (processors in the PRAM-NUMA model terminology) down to synchronous threads interchanging ...
doi:10.15803/ijnc.1.1_21
fatcat:kl3qyj2airbcvbuq42fsdarqde
The Fork95 parallel programming language: Design, implementation, application
1997
International journal of parallel programming
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While farming and parallel divide{and{conquer are directly supported by F ork95 language constructs, pipelining can be easily expressed using existing language features an additional language construct ...
Nevertheless, it supports locally asynchronous computation where desired by the programmer. We present a one{pass compiler, fcc, which compiles Fork95 and C programs to the SB-PRAM machine. ...
Since the SB-PRAM hardware is not yet fully available 3 we use a simulator for the machine that allows to measure exact program execution times. ...
doi:10.1007/bf02700045
fatcat:lwdi6u3qq5apjca7r2kjo3rrda
Towards Parallel Computing on the Internet: Applications, Architectures, Models and Programming Tools
[article]
2006
arXiv
pre-print
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Effects of dynamism and uncertainties that arise in large scale systems are evidently important to understand and yet there is currently little work that addresses this from a parallel computing perspective ...
A number of parallel computing models exist that address this for traditional parallel architectures, and there are a number of emerging models that attempt to do this for large scale Internet-based systems ...
Random Access Machine (APRAM) APRAM is a "fully" asynchronous model [27, 28] . ...
arXiv:cs/0612105v2
fatcat:cgttdbvuurbvbb2zjxqz6h5ehy
Forklight: A control-synchronous parallel programming language
[chapter]
1999
Lecture Notes in Computer Science
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processes in the tradition and notation of PRAM algorithms. ...
It is based on ANSI C and o ers additional constructs to hierarchically divide thread groups into subgroups and manage shared and private address subspaces. ...
An Asynchronous PRAM (see Fig. 1 ). is a MIMD parallel computer with a sequentially consistent shared memory. Each processor runs with its own private clock. ...
doi:10.1007/bfb0100613
fatcat:fzfrsq6gkjdvjc6cjndue752na
XMT-GPU: A PRAM Architecture for Graphics Computation
2008
2008 37th International Conference on Parallel Processing
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We test, through simulation and benchmarking, the potential performance impact of replacing these processors with a fully generalpurpose parallel processor, without the fixed-function graphics hardware ...
Performance is compared for two characteristic shaders running in a fragment-limited GPU benchmark harness and on a cycle-accurate XMT simulator. ...
The simulator gives clock cycles in terms of the interconnection network, which is twice the rate of the TCUs. We had significant freedom in choosing the scale of our base system. ...
doi:10.1109/icpp.2008.35
dblp:conf/icpp/DuBoisLWOV08
fatcat:akjyvib4cngrnhwh6q523s3g6i
Data Independence of Read, Write, and Control Structures in PRAM Computations
2000
Journal of computer and system sciences (Print)
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Our main result is to characterize differences between unbounded fan-in parallelism AC k , bounded fan-in parallelism NC k , and the sequential classes DSPACE(log n) and LOGDCFL in terms of a PRAM's communication ...
In particular, we obtain the first characterizations of NC k and DSPACE(log n) in terms of PRAMs. Finally, we introduce Index-PRAMs, which in some sense have built-in data independence. ...
In particular, we are grateful to Peter Rossmanith for useful suggestions improving presentation and results and to a referee of Journal of Computer and System Sciences for insightful remarks and proposals ...
doi:10.1006/jcss.1999.1665
fatcat:mvcun62f35h6fex7wtz7ttej2m
Soft MOUSETRAP: A Bundled-Data Asynchronous Pipeline Scheme Tolerant to Random Variations at Ultra-Low Supply Voltages
2013
2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems
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OVERVIEW My main research is on asynchronous and mixed-timing digital design. Asynchronous circuits have no centralized or global clock. ...
In particular, it can provide low power (components activated only on-demand, without the need to instrument clock gating, and entirely eliminating the global clock); high performance (some asynchronous ...
processor environment (called XMT, a PRAM-based massively-parallel architecture) and simulation tools. ...
doi:10.1109/async.2013.29
dblp:conf/async/LiuNS13
fatcat:pgi4on5mbffj3fylrygmhghspy
LogP: towards a realistic model of parallel computation
1993
SIGPLAN notices
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A vast body of theoretical research has focused either on overly simplistic models of parallel computation, notably the PRAM, or overly specific models that have few representatives in the real world. ...
Such a model must strike a balance between detail and simplicity in order to reveal important bottlenecks without making analysis of interesting problems intractable. ...
However, the constant factors in this simulation may be large, and would be even larger if the cost of context switching were fully counted. ...
doi:10.1145/173284.155333
fatcat:kb27dlssxzeovfstbxhr27ces4
LogP: towards a realistic model of parallel computation
1993
Proceedings of the fourth ACM SIGPLAN symposium on Principles and practice of parallel programming - PPOPP '93
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A vast body of theoretical research has focused either on overly simplistic models of parallel computation, notably the PRAM, or overly specific models that have few representatives in the real world. ...
Such a model must strike a balance between detail and simplicity in order to reveal important bottlenecks without making analysis of interesting problems intractable. ...
However, the constant factors in this simulation may be large, and would be even larger if the cost of context switching were fully counted. ...
doi:10.1145/155332.155333
dblp:conf/ppopp/CullerKPSSSSE93
fatcat:h36eevyyobcajkblbbj7cj2yv4
Deterministic Computations on a PRAM with Static Processor and Memory Faults
[article]
2018
arXiv
pre-print
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We consider Parallel Random Access Machine (PRAM) which has some processors and memory cells faulty. ...
The simulating PRAM has n processors and m memory cells, and simulates a PRAM with n processors and a constant fraction of m memory cells. ...
The authors thank Krzysztof Diks for discussions of the related faulttolerance issues, and to Piotr Indyk for sharing his insights on the Discrete Fourier Transform and information dispersal. ...
arXiv:1801.00237v2
fatcat:3fbdp74vd5ebfd3okd6vytaxai
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