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Cimple: instruction and memory level parallelism

Vladimir Kiriansky, Haoran Xu, Martin Rinard, Saman Amarasinghe
2018 Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques - PACT '18  
Modern out-of-order processors have increased capacity to exploit instruction level parallelism (ILP) and memory level parallelism (MLP), e.g., by using wide superscalar pipelines and vector execution  ...  to expose ILP and MLP from the instruction stream automatically.  ...  DE-SC0014204, and the Toyota Research Institute under Grant No. LP-C000765-SR. Thanks to Carl Waldspurger for his helpful feedback on the presentation of earlier versions of this manuscript.  ... 
doi:10.1145/3243176.3243185 dblp:conf/IEEEpact/KirianskyXRA18 fatcat:m7vzcvzjufcbbfu3it2vgsoxk4

Cimple: Instruction and Memory Level Parallelism [article]

Vladimir Kiriansky, Haoran Xu, Martin Rinard, Saman Amarasinghe
2018 arXiv   pre-print
Modern out-of-order processors have increased capacity to exploit instruction level parallelism (ILP) and memory level parallelism (MLP), e.g., by using wide superscalar pipelines and vector execution  ...  to expose ILP and MLP from the instruction stream automatically.  ...  Thanks to Carl Waldspurger for his helpful feedback on the presentation of earlier versions of this manuscript.  ... 
arXiv:1807.01624v1 fatcat:p57lcohyh5e2rdebufx5v2lxta