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Chortle-crf: Fast technology mapping for lookup table-based FPGAs
1991
Proceedings of the 28th conference on ACM/IEEE design automation conference - DAC '91
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A new technology mapping algorithm for lookup tablebased Field Programmable Gate Arrays (FPGA) is presented. ...
The major innovation is a method for choosing gate-level decompositions based on bin packing. ...
Note that Chortle-crf is capable of implementing networks as circuits of K- input lookup tables for values of K from 2 to 10. ...
doi:10.1145/127601.127670
dblp:conf/dac/FrancisRV91
fatcat:xrnrv2cvpvefloh42hddl4mbmi
DAG-Map: graph-based FPGA technology mapping for delay optimization
1992
IEEE Design & Test of Computers
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In this paper, we present a graph based technology mapping algorithm, called DAG-Map, for delay optimization in lookup-table based FPGA designs. ...
In this paper, we present a graph based technology mapping algorithm, called DAG-Map, for delay optimization in lookup-table based FPGA design. ...
We thank Professor Jonathan Rose and Robert Francis for providing the Chortle programs and necessary assistance for our comparative study. ...
doi:10.1109/54.156154
fatcat:kmlfatq3abebdeqfcspqusynae
On area/depth trade-off in LUT-based FPGA technology mapping
1993
Proceedings of the 30th international on Design automation conference - DAC '93
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In this paper we study the area and depth trade-off in LUT based FPGA technology mapping. ...
For the area minimization step, we have developed an optimal algorithm for computing an area-minimum mapping solution without node duplication. ...
The lookup table (LUT) based FPGAs are produced by several FPGA manufacturers [16, 8] , in which the basic programmable logic block is a K-input lookup table that can implement any Boolean function of ...
doi:10.1145/157485.164675
dblp:conf/dac/CongD93
fatcat:bbs6i5otcnfjdlwhusn6nlwglu
On area/depth trade-off in LUT-based FPGA technology mapping
1994
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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In this paper we study the area and depth trade-off in LUT based FPGA technology mapping. ...
For the area minimization step, we have developed an optimal algorithm for computing an area-minimum mapping solution without node duplication. ...
The lookup table (LUT) based FPGAs are produced by several FPGA manufacturers [16, 8] , in which the basic programmable logic block is a K-input lookup table that can implement any Boolean function of ...
doi:10.1109/92.285741
fatcat:4zqdr3xwzzbzbgssgxsogot4pq
Boolean matching for LUT-based logic blocks with applications to architecture evaluation and technology mapping
2001
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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(FPGA) technology mapping. ...
In this paper, we present new Boolean matching methods for lookup table (LUT)-based programmable logic blocks (PLBs) and their applications to PLB architecture evaluations and field programmable gate array ...
Kelem from Xilinx for providing the test suite used in Section VI-A. ...
doi:10.1109/43.945303
fatcat:suitjdhcy5b7fhjtgz63ygayga
DP-FPGA: An FPGA Architecture Optimized for Datapaths
1996
VLSI design (Print)
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This paper presents a new Field-Programmable Gate Array (FPGA) architecture which reduces the density gap between FPGAs and Mask-Programmed Gate Arrays (MPGAs) for datapath oriented circuits. ...
Experimental results show that the block with the smallest estimated area contains the following features: a lookup table with four read ports, a dedicated carry chain using a bidirectional four-bit carry ...
Partition remaining combinational logic
into K-input lookup tables using chortle-crf
[2].
4. Search graph of lookup tables for multi-
plexer functions. ...
doi:10.1155/1996/95942
fatcat:iv4bulcioja7xlsjlfxw34yoce
Technology mapping for k/m-macrocell based FPGAs
2000
Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays - FPGA '00
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In this paper, we study the technology mapping problem for a novel FPGA architecture that is based on k-input single-output PLA-like cells, or, k/m-macrocells. ...
We develop a very efficient technology mapping algorithm, k_m_flow, for this new type of architecture. The experiment results show our algorithm can achieve depthoptimality in practically all cases. ...
Vaughn Betz from Right Track Corp. for their helpful comments and discussion. ...
doi:10.1145/329166.329179
dblp:conf/fpga/CongHY00
fatcat:frzwavxmi5fhbeuejkwg6uhtme
Technology mapping and architecture evalution for k/m-macrocell-based FPGAs
2005
ACM Transactions on Design Automation of Electronic Systems
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with the traditional k-input single-output lookup table-(k-LUT-) based FPGAs. ...
In this article, we study the technology mapping problem for a novel field-programmable gate array (FPGA) architecture that is based on k-input single-output programmable logic array-(PLA-) like cells, ...
Vaughn Betz for their helpful comments and discussion. ...
doi:10.1145/1044111.1044113
fatcat:hroeclumvnbv3fwjocgzt7dxja
GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches
2007
Proceedings - Design Automation Conference
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Previous poweraware technology mapping algorithms for FPGAs have not taken into account the glitch power reduction. ...
To the best of our knowledge, this is the first work that explicitly reduces glitch power during technology mapping for FPGAs. ...
FPGA technology mapping algorithms can be classified into the following categories: area minimization algorithms, including Chortle-crf [4] and MIS-pga [5] ; delay minimization algorithms, including ...
doi:10.1109/dac.2007.375179
fatcat:u6xmbsphgzgenphk3jj5hsctk4
GlitchMap
2007
Proceedings - Design Automation Conference
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Previous poweraware technology mapping algorithms for FPGAs have not taken into account the glitch power reduction. ...
To the best of our knowledge, this is the first work that explicitly reduces glitch power during technology mapping for FPGAs. ...
FPGA technology mapping algorithms can be classified into the following categories: area minimization algorithms, including Chortle-crf [4] and MIS-pga [5] ; delay minimization algorithms, including ...
doi:10.1145/1278480.1278562
dblp:conf/dac/ChengCW07
fatcat:hrcncbixs5bgdaotpfp3k3dt3e
Combinational logic synthesis for LUT based field programmable gate arrays
1996
ACM Transactions on Design Automation of Electronic Systems
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The most widely used FPGAs are LUT based FPGAs, in which the basic logic element is a K-input one-output lookup-table (LUT) that can implement any Boolean function of up to K variables. ...
This article summarizes the research results on combinational logic synthesis for LUT based FPGAs under a coherent framework. ...
The most common approach of implementing the basic logic element in an SRAM based FPGA is via a 2 K -bit SRAM cell, which represents a K-input one-output lookup-table (LUT), capable of realizing any Boolean ...
doi:10.1145/233539.233540
fatcat:q62vuvv565h6hmzkfp67be6urm
OBDD-based function decomposition: algorithms and implementation
1996
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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These techniques are applied to the synthesis of look-up table based field programmable gate arrays and results are presented. ...
This paper presents algorithms for disjunctive and nondisjunctive decomposition of Boolean functions and Boolean methods for identifying common subfunctions from multiple Boolean functions. ...
We describe an OBDD-based decomposition program, called FGSyn, that integrates the technology-independent and technology-mapping processes for LUT-based FPGAs. ...
doi:10.1109/43.511577
fatcat:v4zj2f5vq5hb7bilphkfila3bq
Performance-driven mapping for CPLD architectures
2001
Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays - FPGA '01
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Index Terms-Complex programmable logic device (CPLD) architecture, technology mapping. ...
We present a performance-driven programmable logic array mapping algorithm (PLAmap) for complex programmable logic device architectures consisting of a large number of PLA-style logic cells. ...
The algorithmic flow of TEMPLA included three phases: optimal tree mapping, heuristic partial collapsing, and bin packing, which were similar to that of the Chortle-crf technology mapper [7] for LUT-based ...
doi:10.1145/360276.360296
dblp:conf/fpga/ChenCEH01
fatcat:ofm6nzuy4ze4pkr6mfe4rs7guq
Performance-driven mapping for cpld architectures
2003
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Index Terms-Complex programmable logic device (CPLD) architecture, technology mapping. ...
We present a performance-driven programmable logic array mapping algorithm (PLAmap) for complex programmable logic device architectures consisting of a large number of PLA-style logic cells. ...
The algorithmic flow of TEMPLA included three phases: optimal tree mapping, heuristic partial collapsing, and bin packing, which were similar to that of the Chortle-crf technology mapper [7] for LUT-based ...
doi:10.1109/tcad.2003.818120
fatcat:yywqxrwjcrdjdm5tlzyof57c2e
Area-speed tradeoffs for hierarchical field-programmable gate arrays
1996
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays - FPGA '96
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This paper investigates area-speed trade-offs for Hierarchical FPGA (HFPGA) architectures. ...
These experiments demonstrate that HFPGAs can achieve both better area and speed than symmetrical FPGA architectures [2]. ...
The experimental procedures for HFPGAs and symmetrical FPGAs were: i) Technology independent optimization using SIS [12] . ii) Technology mapping into 4-input LUT logic blocks using chortle-crf [13] ...
doi:10.1145/228370.228378
dblp:conf/fpga/ChanL96
fatcat:l6by44fbzvcmfcdf244czwfc5y
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