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Chortle-crf: Fast technology mapping for lookup table-based FPGAs

Robert Francis, Jonathan Rose, Zvonko Vranesic
1991 Proceedings of the 28th conference on ACM/IEEE design automation conference - DAC '91  
A new technology mapping algorithm for lookup tablebased Field Programmable Gate Arrays (FPGA) is presented.  ...  The major innovation is a method for choosing gate-level decompositions based on bin packing.  ...  __y a) without gate decomposition b) with gate decomposition b) circuit of 5-input lookup tables Figure 2.  ... 
doi:10.1145/127601.127670 dblp:conf/dac/FrancisRV91 fatcat:xrnrv2cvpvefloh42hddl4mbmi

DAG-Map: graph-based FPGA technology mapping for delay optimization

K.-C. Chen, J. Cong, Y. Ding, A.B. Kahng, P. Trajmar
1992 IEEE Design & Test of Computers  
In this paper, we present a graph based technology mapping algorithm, called DAG-Map, for delay optimization in lookup-table based FPGA designs.  ...  In this paper, we present a graph based technology mapping algorithm, called DAG-Map, for delay optimization in lookup-table based FPGA design.  ...  We thank Professor Jonathan Rose and Robert Francis for providing the Chortle programs and necessary assistance for our comparative study.  ... 
doi:10.1109/54.156154 fatcat:kmlfatq3abebdeqfcspqusynae

The effect of logic block architecture on FPGA performance

S. Singh, J. Rose, P. Chow, D. Lewis
1992 IEEE Journal of Solid-State Circuits  
This paper explores the effect of logic block architecture on the speed of a field-programmable gate array (FPGA).  ...  Four classes of logic block architecture are investigated: NAND gates, multiplexer configurations, lookup tables, and wide-input AND-OR gates.  ...  tables: The technology mapping for lookup tables is done by the Chortle-d [13] technology mapping program.  ... 
doi:10.1109/4.121549 fatcat:fvddsl745fh3rcmlctenzfdmzq

The effect of logic block complexity on area of programmable gate arrays

J. Rose, R.J. Francis, P. Chow, D. Lewis
1989 1989 Proceedings of the IEEE Custom Integrated Circuits Conference  
It is similar to a gate array in structure, but can be field-programmed to specify the function of the basic logic blocks and their interconnection.  ...  This paper explores the tradeoff between the area of a Programmable Gate Array (PGA) and the functionality of its logic block.  ...  This is sometimes called technology mapping [Detj87], and is a more difficult problem for PGA logic blocks with table-lookup logic functions.  ... 
doi:10.1109/cicc.1989.56691 fatcat:esagaybpzzfy7eed3kl6uxgomm

Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency

J. Rose, R.J. Francis, D. Lewis, P. Chow
1990 IEEE Journal of Solid-State Circuits  
The experiments are based on logic blocks that use lookup tables for implementing combinational logic.  ...  This paper examines the relationship between the functionality of a field-programmable gate array (FPGA) logic block and the area required to implement digital circuits using that logic block.  ...  Young of Zymos for supplying the circuits and cell functional descriptions.  ... 
doi:10.1109/4.62145 fatcat:klcj5dokwrcr5ooxskadxnz4hu

FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs

J. Cong, Yuzheng Ding
1994 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
A6struct- The field programmable gate-array (FPGA) has become an important technology in VLSI ASIC designs.  ...  In the past a few years, a number of heuristic algorithms have been proposed for technology mapping in lookup-table (LUT) based FPGA designs, but none of them guarantees optimal solutions for general Boolean  ...  ACKNOWLEDGMENT The authors thank Professor Jonathan Rose, Robert Francis, and Rajeev Murgai for their assistance in the authors' comparative study.  ... 
doi:10.1109/43.273754 fatcat:x4br6zft45e7pozkaj3v4pigj4

Optimization methods for lookup-table-based FPGAs using transduction method

Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga
1995 Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM) - ASP-DAC '95  
Acknowledgements We would thank Shuzo Yajima for permitting to use the SBDD package developed by his group.  ...  This research was supported by International Research Program : Joint Research from the Ministry of Education, Science and Culture in Japan.  ...  Introduction In recent years, Field Programmable Gate Arrays(FPGAs) have emerged as an attractive means to implement low volume applications and prototypes due to their low cost, reprogrammability and  ... 
doi:10.1145/224818.224921 dblp:conf/aspdac/YamashitaKM95 fatcat:isxkvpehkvaqjbbnfiknmfyaaa

Simultaneous logic decomposition with technology mapping in FPGA designs

Gang Chen, Jason Cong
2001 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays - FPGA '01  
Conventional technology mapping algorithms for SRAM-based Field Programmable Gate Arrays (FPGAs) are normally carried out on a fixed logic decomposition of a circuit.  ...  In this paper, we present an algorithm named SLDMap that performs delay-minimized technology mapping on a large set of decompositions and simultaneously controls the mapping area under delay constraints  ...  This work is partially supported by Actel, Lucent Technology and Xilinx under the California Micro Program and the NSF under grant MIP-9357582.  ... 
doi:10.1145/360276.360298 dblp:conf/fpga/ChenC01 fatcat:jn7wlf2qgvdcjjg3zqbqajexni

DP-FPGA: An FPGA Architecture Optimized for Datapaths

Don Cherepacha, David Lewis
1996 VLSI design (Print)  
This paper presents a new Field-Programmable Gate Array (FPGA) architecture which reduces the density gap between FPGAs and Mask-Programmed Gate Arrays (MPGAs) for datapath oriented circuits.  ...  Experimental results show that the block with the smallest estimated area contains the following features: a lookup table with four read ports, a dedicated carry chain using a bidirectional four-bit carry  ...  The CAD tools developed are based around the Chortle lookup table mapper.  ... 
doi:10.1155/1996/95942 fatcat:iv4bulcioja7xlsjlfxw34yoce

On area/depth trade-off in LUT-based FPGA technology mapping

J. Cong, Yuzheng Ding
1994 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
In this paper we study the area and depth trade-off in LUT based FPGA technology mapping.  ...  Starting from a depth-optimal mapping solution, we perform a number of depth relaxation operations to obtain a new network with bounded increase in depth and advantageous to subsequent re-mapping for area  ...  Introduction The Field programmable gate array (FPGA) has become a very popular technology in VLSI ASIC design and system prototyping.  ... 
doi:10.1109/92.285741 fatcat:4zqdr3xwzzbzbgssgxsogot4pq

On area/depth trade-off in LUT-based FPGA technology mapping

Jason Cong, Yuzheng Ding
1993 Proceedings of the 30th international on Design automation conference - DAC '93  
In this paper we study the area and depth trade-off in LUT based FPGA technology mapping.  ...  Starting from a depth-optimal mapping solution, we perform a number of depth relaxation operations to obtain a new network with bounded increase in depth and advantageous to subsequent re-mapping for area  ...  Introduction The Field programmable gate array (FPGA) has become a very popular technology in VLSI ASIC design and system prototyping.  ... 
doi:10.1145/157485.164675 dblp:conf/dac/CongD93 fatcat:bbs6i5otcnfjdlwhusn6nlwglu

LUT-based FPGA technology mapping under arbitrary net-delay models

Jason Cong, Yuzheng Ding, Tong Gao, Kuang-Chien Chen
1994 Computers & graphics  
The field programmable gate-array (FPGA) has become an important technology in VLSI ASIC designs.  ...  Most existing algorithms for performance-driven technology mapping for Lookup-table (LUT) based FPGA designs are based on the unit-delay model.  ...  -21- Acknowledgment This research is partially supported by a grant from Xilinx Inc. under the State of California MICRO program, a grant from Fujitsu America, and the National Science Foundation Young  ... 
doi:10.1016/0097-8493(94)90063-9 fatcat:k6p7olszkvecxlsakt5iz7nwnm

Technology mapping for large complex PLDs

Jason Helge Anderson, Stephen Dean Brown
1998 Proceedings of the 35th annual conference on Design automation conference - DAC '98  
In this paper we present a new technology mapping algorithm for use with complex PLDs (CPLDs), which consist of a large number of PLA-style logic blocks.  ...  Although the traditional synthesis approach for such devices uses two-level minimization, the complexity of recently-produced CPLDs has resulted in a trend toward multi-level synthesis.  ...  Jack Kouloheris for providing code for the DDMAP [11] algorithm.  ... 
doi:10.1145/277044.277220 dblp:conf/dac/AndersonB98 fatcat:pj6cqzowencl5mw72lci4t6jwi

Technology mapping for k/m-macrocell based FPGAs

Jason Cong, Hui Huang, Xin Yuan
2000 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays - FPGA '00  
In this paper, we study the technology mapping problem for a novel FPGA architecture that is based on k-input single-output PLA-like cells, or, k/m-macrocells.  ...  We develop a very efficient technology mapping algorithm, k_m_flow, for this new type of architecture. The experiment results show our algorithm can achieve depthoptimality in practically all cases.  ...  Vaughn Betz from Right Track Corp. for their helpful comments and discussion.  ... 
doi:10.1145/329166.329179 dblp:conf/fpga/CongHY00 fatcat:frzwavxmi5fhbeuejkwg6uhtme

Depth optimal incremental mapping for field programmable gate arrays

Jason Cong, Hui Huang
2000 Proceedings of the 37th conference on Design automation - DAC '00  
In this paper, we study the incremental t echnology mapping problem for lookup-table (LUT) based Field Programmable Gate Arrays (FPGAs) under incremental changes.  ...  Given a gate-level network, a mapping solution associated with it, and a sequence of changes to the original network, we c ompute a new mapping solution by modifying the existing one.  ...  Many technology mapping algorithms for FPGAs have been published in recent years, for example, tree-based Chortle-family algorithms by Francis et al.  ... 
doi:10.1145/337292.337422 dblp:conf/dac/CongH00 fatcat:f2ux7y5b75c4pntwmlfdp2y54e
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