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MMNoC: Embedding Memory Management Units into Network-on-Chip for Lightweight Embedded Systems

Hyeonguk Jang, Kyuseung Han, Sukho Lee, Jae-Jin Lee, Woojoo Lee
2019 IEEE Access  
that support multiprocessing.  ...  INDEX TERMS Network-on-chip, NoC, memory management unit, MMU, embedded system.  ...  FIGURE 9 . 9 The proposed NI architecture that extends beyond the traditional NI designs. FIGURE 10 . 10 Hardware platform for verification.  ... 
doi:10.1109/access.2019.2923219 fatcat:hejulkauuvcljan4qiucdd2nzy

Selected Research from Hot Chips 24

Christos Kozyrakis, Rumi Zahir
2013 IEEE Micro  
The final trend is the appearance of chips that take established instruction sets beyond their traditional application domains, smartphones for x86 and servers for ARM.  ...  He was also one of the Intel Itanium Processor instruction set architects contributing to privileged instruction set, multiprocessing, memory ordering, and interrupt architecture.  ... 
doi:10.1109/mm.2013.44 fatcat:xbpxyxfbzbbldkvk45rrghufxa

The AMD opteron processor for multiprocessor servers

C.N. Keltcher, K.J. McGrath, A. Ahmed, P. Conway
2003 IEEE Micro  
Fred Weber, Bill Hughes, Ramsey Haddad, Dave Christie, Scott White, Gerald Zuraski, Phil Madrid, Kelvin Goveas, Ashraf Ahmed, Michael Clark, Hongwen Gao, Bruce Holloway, Richard Klass, Dave Kroesche, and  ...  Figure 10 . 10 Scaling beyond eight-way multiprocessing using an external switch.  ...  Scaling beyond eight-way multiprocessing We designed Opteron for use as a building block for highly scalable and reliable enter-prise servers. 7, 8 It is designed to scale beyond eight ways by combining  ... 
doi:10.1109/mm.2003.1196116 fatcat:hb22yv223rg37lg5iwtz7yuzu4

Piranha

Luiz André Barroso, Kourosh Gharachorloo, Robert McNamara, Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets, Ben Verghese
2000 SIGARCH Computer Architecture News  
Piranha also integrates further on-chip functionality to allow for scalable multiprocessor configurations to be built in a glueless and modular fashion.  ...  The abundance of explicit thread-level parallelism in commercial workloads, along with advances in semiconductor integration density, identify chip multiprocessing (CMP) as potentially the most promising  ...  The following people have also made significant technical contributions to Piranha: Joan Pendleton wrote the initial Verilog for the Alpha core, Dan Scales helped with the inter-chip coherence protocol  ... 
doi:10.1145/342001.339696 fatcat:4vkvpcl3fbbyroknoobobfd4ye

Piranha

Luiz André Barroso, Kourosh Gharachorloo, Robert McNamara, Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets, Ben Verghese
2000 Proceedings of the 27th annual international symposium on Computer architecture - ISCA '00  
Piranha also integrates further on-chip functionality to allow for scalable multiprocessor configurations to be built in a glueless and modular fashion.  ...  The abundance of explicit thread-level parallelism in commercial workloads, along with advances in semiconductor integration density, identify chip multiprocessing (CMP) as potentially the most promising  ...  The following people have also made significant technical contributions to Piranha: Joan Pendleton wrote the initial Verilog for the Alpha core, Dan Scales helped with the inter-chip coherence protocol  ... 
doi:10.1145/339647.339696 fatcat:5j2s3ywecjaeljdv2jsczyb3wa

Trends in multicore DSP platforms

Lina Karam, Ismail Alkamal, Alan Gatherer, Gene Frantz, David Anderson, Brian Evans
2009 IEEE Signal Processing Magazine  
Since 1996, he has been on the faculty at The University of Texas at Austin, where he is currently an electrical and computer engineering professor. In 1997, he won the U.S. NSF CAREER Award.  ...  Note that the latest in the OMAP line has both multicore ARM (symmetric multiprocessing) and DSP (for heterogeneous multiprocessing).  ...  Multicore DSP platforms can also be categorized as symmetric multiprocessing (SMP) platforms and asymmetric multiprocessing (AMP) platforms.  ... 
doi:10.1109/msp.2009.934113 fatcat:2hsjudqn7nfclbjhm5lkivi2ee

Cache-Coherent Heterogeneous Multiprocessing as Basis for Streaming Applications [chapter]

Jos van Eijndhoven, Jan Hoogerbrugge, M.N. Jayram, Paul Stravers, Andrei Terechko
2005 Philips Research  
These chips will support the execution of a mix of concurrent applications that are not known in detail at chip design time.  ...  ease the programming effort multiprocessor computers have employed cache coherent share memory for decades, abstracting the average programmer from system complexity issues such as multiple processors and  ...  The use of multi-threading applications is becoming more-and-more accepted as generic programming model, as the trend towards chip-multiprocessing and CPU's with multi-thread facilities is picked up by  ... 
doi:10.1007/1-4020-3454-7_3 fatcat:f65fpatwlrdipi27dc3ongnxze

A Brief History of Multiprocessors and EDA

Sandeep Shukla, Prabhat Mishra, Zeljko Zilic
2011 IEEE Design & Test of Computers  
A concomitant focus on multiple cores on the same chip started with IBM, Sun, Intel, and AMD all announcing multicore products.  ...  In the early 2000s, Intel and AMD went head to head to break the 1-GHz barrier; that led to 2 GHz and beyond, till the power consumption problem arose.  ... 
doi:10.1109/mdt.2011.50 fatcat:vdgvvsrrb5bsvilatyhtpw7yda

Multiprocess 3D printing for increasing component functionality

E. MacDonald, R. Wicker
2016 Science  
developments and has had a profound impact on the authors and their research. 10 .1126/science.aaf2093  ...  ACKNOWLEDGMENTS We acknowledge NSF, the Department of Defense, the National Institute of Standards and Technology, NASA, the Department of Energy, and the intelligence community for support that enabled  ...  When a printed trace extends to a pin of a chip, an electrical connection forms without the requirement of high-temperature soldering.  ... 
doi:10.1126/science.aaf2093 pmid:27708075 fatcat:fbhg5f6rsbgs3mlquzefziw77q

Multi-core processors - An overview [article]

Balaji Venu
2011 arXiv   pre-print
Microprocessors have revolutionized the world we live in and continuous efforts are being made to manufacture not only faster chips but also smarter ones.  ...  This paper briefs on evolution of multi-core processors followed by introducing the technology and its advantages in today's world.  ...  Also along side OpenMP (Open Multiprocessing), an application programming interface which supports multiprocessing programming in C, C++ and Fortran provides directives for efficient multithreaded codes  ... 
arXiv:1110.3535v1 fatcat:terjmabsznhrdcvwdg4ddhyboa

Trends in shared memory multiprocessing

P. Stenstrom, E. Hagersten, D.J. Lilja, M. Martonosi, M. Venugopal
1997 Computer  
The second step is to begin filling gaps in programming models and architectures for shared memory multiprocessing.  ...  These machines, which typically have fewer than 16 Current application and technology trends are causing researchers and developers to revisit shared memory multiprocessing.  ...  We also thank the anonymous reviewers and those at Silicon Graphics who contributed their thoughts: Dan Lenoski, Brond Larson, Woody Lichtenstein, John McCalpin, and Jeff McDonald.  ... 
doi:10.1109/2.642814 fatcat:mhsgglxwfvdrtc4c4ap6eshxxa

Multiprocessing design verification methodology for Motorola MPC74XX PowerPC microprocessor

Jen-Tien Yen, Qichao Richard Yin
2000 Proceedings of the 37th conference on Design automation - DAC '00  
The problem is getting worse as the design complexity increases and more cache structures are integrated into one single chip.  ...  Multiprocessing (MP) design verification has been one of the bottlenecks for high performance microprocessor design projects.  ...  This gave us the benefit of continuous and extensive simulation on MP logic using either unit or chip/system model until tapeout and beyond.  ... 
doi:10.1145/337292.337755 dblp:conf/dac/YenY00 fatcat:oshzysltpnfflpzkatdu6h6qvm

Horus: Large-Scale Symmetric Multiprocessing for Opteron Systems

R. Kota, R. Oehler
2005 IEEE Micro  
Figure 1 shows the inter- Work on Symmetric Multiprocessing Systems Both research and industry have produced SMP systems.  ...  The RMPEs have on-chip tags to track data cached in off-chip memory.  ...  All arrays (on and off chip) have error checking and correction that supports singlebit error correction, double-bit error detection, and scrubbing.  ... 
doi:10.1109/mm.2005.28 fatcat:3ibu2e762nai5ietfaj53ztu4a

The Cell Broadband Engine: Exploiting Multiple Levels of Parallelism in a Chip Multiprocessor

Michael Gschwind
2007 International journal of parallel programming  
As CMOS feature sizes continue to shrink and traditional microarchitectural methods for delivering high performance (e.g., deep pipelining) become too expensive and power-hungry, chip multiprocessors (  ...  By taking advantage of opportunities at all levels of the system, this CMP revolutionizes parallel architectures to deliver previously unattained levels of single chip performance.  ...  embracing chip multiprocessing.  ... 
doi:10.1007/s10766-007-0035-4 fatcat:zcndew73k5bevgjnuc3h3lbtya

Parallelism exploitation in superscalar multiprocessing

N.-P. Lu, C.-P. Chung
1998 IEE Proceedings - Computers and digital Techniques  
It was observed that the instruction-level and task-level parallelism in programs can be exploited well by a moderate degree of superscalar processing and a high degree of multiprocessing.  ...  This simulator models both a superscalar processor that can exploit instruction-level parallelism, and a shared-memory multiprocessor system that can exploit task-level parallelism.  ...  the instruction scheduling window to grow beyond basic block boundaries.  ... 
doi:10.1049/ip-cdt:19981955 fatcat:ih24325o5jcijevm5hwntouove
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