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Chip Placement with Deep Reinforcement Learning [article]

Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan, Joe Jiang, Ebrahim Songhori, Shen Wang, Young-Joon Lee, Eric Johnson, Omkar Pathak, Sungmin Bae, Azade Nazi, Jiwoo Pak (+10 others)
2020 arXiv   pre-print
To achieve these results, we pose placement as a Reinforcement Learning (RL) problem and train an agent to place the nodes of a chip netlist onto a chip canvas.  ...  In this work, we present a learning-based approach to chip placement, one of the most complex and time-consuming stages of the chip design process.  ...  To achieve these results, we pose placement as a Reinforcement Learning (RL) problem and train an agent to place the nodes of a chip netlist onto a chip canvas.  ... 
arXiv:2004.10746v1 fatcat:v5urekya2fgw3dcxbp3hskhpr4

Placement Optimization with Deep Reinforcement Learning [article]

Anna Goldie, Azalia Mirhoseini
2020 arXiv   pre-print
In this paper, we start by motivating reinforcement learning as a solution to the placement problem. We then give an overview of what deep reinforcement learning is.  ...  Finally, we describe lessons we have learned from training deep reinforcement learning policies across a variety of placement optimization problems.  ...  ACKNOWLEDGMENTS We would like to thank our amazing collaborators on deep reinforcement learning for placement research, including Ebrahim Songhori, Joe Jiang, Shen Wang, Hieu Pham, Yanqi Zhou, Will Hang  ... 
arXiv:2003.08445v1 fatcat:msjrsgq4ava4xfnaduhak7ocz4

Routing and Placement of Macros using Deep Reinforcement Learning [article]

Mrinal Mathur
2022 arXiv   pre-print
Looking at these prior problems we wanted to introduce a new method using Reinforcement Learning where we train the model to place the nodes of a chip netlist onto a chip canvas.  ...  Chip placement has been one of the most time consuming task in any semi conductor area, Due to this negligence, many projects are pushed and chips availability in real markets get delayed.  ...  Also, Ronita Mitra from Qualcomm for helping us with the inital Placement on EDA tools and visualizations.  ... 
arXiv:2205.09289v1 fatcat:dwli4lr4kncyhdiym6f33ylvju

Flexible Multiple-Objective Reinforcement Learning for Chip Placement [article]

Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang (+2 others)
2022 arXiv   pre-print
Recently, successful applications of reinforcement learning to chip placement have emerged. Pretrained models are necessary to improve efficiency and effectiveness.  ...  This paper proposes flexible multiple-objective reinforcement learning (MORL) to support objective functions with inference-time variable weights using just a single pretrained model.  ...  A state-of-the-art placement tool that employs the power of machine learning, deep reinforcement learning (DRL), and representation learning has been developed by Mirhoseini et. al [13, 14] .  ... 
arXiv:2204.06407v1 fatcat:sobyaee45jaidobvcu5rfbxh2y

Machine Learning for Systems

Heiner Litz, Milad Hashemi
2020 IEEE Micro  
In "RELEQ: A Reinforcement Learning Approach for Automatic Deep Quantization of Neural Networks," the authors describe a reinforcement learning mechanism to optimize deep neural network architectures.  ...  Our issue concludes with an article proposing machine learning techniques to improve the security of hardware systems, particularly networkson-chip.  ... 
doi:10.1109/mm.2020.3016551 fatcat:7lbbknjtmjamha2ek5fnc2tbem

A Transferable Approach for Partitioning Machine Learning Models on Multi-Chip-Modules [article]

Xinfeng Xie, Prakash Prabhu, Ulysse Beaugnon, Phitchaya Mangpo Phothilimthana, Sudip Roy, Azalia Mirhoseini, Eugene Brevdo, James Laudon, Yanqi Zhou
2021 arXiv   pre-print
In this paper, we present a strategy using a deep reinforcement learning (RL) framework to emit a possibly invalid candidate partition that is then corrected by a constraint solver.  ...  Multi-Chip-Modules (MCMs) reduce the design and fabrication cost of machine learning (ML) accelerators while delivering performance and energy efficiency on par with a monolithic large chip.  ...  These shortcomings motivate us to develop our constrained reinforcement learning method detailed in Section 4, which combines the reinforcement learning method with the constraint solver to efficiently  ... 
arXiv:2112.04041v1 fatcat:2m64g7rdabevdpoc4xi6io6fa4

The Deep Learning Revolution and Its Implications for Computer Architecture and Chip Design [article]

Jeffrey Dean
2019 arXiv   pre-print
It also discusses some of the ways that machine learning may also be able to help with some aspects of the circuit design process.  ...  The past decade has seen a remarkable series of advances in machine learning, and in particular deep learning approaches based on artificial neural networks, to improve our abilities to build more accurate  ...  By having a reinforcement learning algorithm learn to "play" the game of placement and routing, either in general across many different ASIC designs, or for a particular ASIC design, with a reward function  ... 
arXiv:1911.05289v1 fatcat:obp23uohjza3vclxyvwmes2e7i

Optimizing Routerless Network-on-Chip Designs: An Innovative Learning-Based Framework [article]

Ting-Ru Lin, Drew Penney, Massoud Pedram, Lizhong Chen
2019 arXiv   pre-print
This paper proposes a novel deep reinforcement framework, taking routerless networks-on-chip (NoC) as an evaluation case study.  ...  The framework learns (near-)optimal loop placement for routerless NoCs with various design constraints.  ...  Reinforcement Learning Challenges Several considerations apply to deep reinforcement learning in any domain.  ... 
arXiv:1905.04423v1 fatcat:dlfrvxriqrevjbo5b6uwst2bcq

Survey of Machine Learning for Electronic Design Automation

Kevin Immanuel Gubbi, Sayed Aresh Beheshti-Shirazi, Tyler Sheaves, Soheil Salehi, Sai Manoj PD, Setareh Rafatirad, Avesta Sasan, Houman Homayoun
2022 Proceedings of the Great Lakes Symposium on VLSI 2022  
An increase in demand for semiconductor ICs, recent advancements in machine learning, and the slowing down of Moore's law have all contributed to the increased interest in using Machine Learning (ML) to  ...  They are utilized in Synthesis, Physical Design (Floorplanning, Placement, Clock Tree Synthesis, Routing), IR drop analysis, Static Timing Analysis (STA), Design for Test (DFT), Power Delivery Network  ...  The Reinforcement Learning (RL) solutions are independent of data samples and are based on the interaction of an agent with an environment.  ... 
doi:10.1145/3526241.3530834 fatcat:zixyjpof45b25kvlootimwrusu

Automated Atomic Silicon Quantum Dot Circuit Design via Deep Reinforcement Learning [article]

Robert Lupoiu, Samuel S. H. Ng, Jonathan A. Fan, Konrad Walus
2022 arXiv   pre-print
The automated designer is capable of navigating the complex, hyperdimensional design spaces of arbitrarily sized design areas and truth tables by employing a tabula rasa double-deep Q-learning reinforcement  ...  learning algorithm.  ...  Overview of the double-deep Q-learning iterative SiDB dot placement automated design procedure.  ... 
arXiv:2204.06288v1 fatcat:ai4t2nbr6facjmkuxpyu3tybty

Knowledge-based neural compact modeling towards autonomous technology development

Soogine Chong
2021 Zenodo  
Outline Motivation Introduction to neural network model Knowledge-based NN model Training with inductive bias Building prior knowledge from multiple tasks End-to-end autonomous technology development Goal  ...  ., "GCN-RL circuit designer: Transferable transistor sizing with graph neural networks and reinforcement learning," DAC, 2020] [https://ai.googleblog.com/2020/04/chip-design-with-deep-reinforcement.html  ...  AI in IC Design -Examples [Mirhoseini et al., "A graph placement methodology for fast chip design," Nature, 2021] [H.  ... 
doi:10.5281/zenodo.5642865 fatcat:vnnvghjzkjhazmo6dofqmbwyhq

Reinforcement Learning Approach for Mapping Applications to Dataflow-Based Coarse-Grained Reconfigurable Array [article]

Andre Xian Ming Chang, Parth Khopkar, Bashar Romanous, Abhishek Chaurasia, Patrick Estep, Skyler Windh, Doug Vanesko, Sheik Dawood Beer Mohideen, Eugenio Culurciello
2022 arXiv   pre-print
In this work we propose a Reinforcement Learning framework with Global Graph Attention (GGA) module and output masking of invalid placements to find and optimize instruction schedules.  ...  The graph neural network creates embeddings of the SDFs and the attention block is used to model sequential operation placement.  ...  A review of various machine learning approaches is presented in [29] which including reinforcement learning for chip design.  ... 
arXiv:2205.13675v1 fatcat:fmm3dk3oibcgnjriasgds2c7gy

Collaborative Distillation Meta Learning for Simulation Intensive Hardware Design [article]

Haeyeon Kim, Minsu Kim, Joungho Kim, Jinkyoo Park
2022 arXiv   pre-print
Deep reinforcement learning (DRL) has shown promising performance in various hardware design problems.  ...  The collaborative distillation scheme with equivariant label transformation imposes the action-permutation (AP)-equivariant nature of placement problems, which not only improves sample efficiency but also  ...  Deep Reinforcement Learning-based Methods.  ... 
arXiv:2205.13225v1 fatcat:vm3252vdxbbsbaz54eltwiukmm

Delving into Macro Placement with Reinforcement Learning [article]

Zixuan Jiang, Ebrahim Songhori, Shen Wang, Anna Goldie, Azalia Mirhoseini, Joe Jiang, Young-Joon Lee, David Z. Pan
2021 arXiv   pre-print
Reinforcement learning (RL) methods have demonstrated superhuman performance on the macro placement. In this paper, we propose an extension to this prior work (Mirhoseini et al., 2020).  ...  We replace the force-directed method with DREAMPlace for placing standard cells in the RL environment. We also compare our improved method with other academic placers on public benchmarks.  ...  Standard cell placement follows as a standard operator afterwards. C. Macro placement with reinforcement learning Mirhoseini et al. [1] propose to place macros using RL methods.  ... 
arXiv:2109.02587v1 fatcat:xumvycd5bve5dgzvheprfhdnwu

Accelerate lithography improvement for high performance computing

John Y. Chen, Kurt G. Ronse, Paolo A. Gargini, Eric Hendrickx, Patrick P. Naulleau, Toshiro Itani
2018 International Conference on Extreme Ultraviolet Lithography 2018  
Artificial intelligence (AI) with deep learning is taking off based on High Performance Computing (HPC) engines fueled by "Big Data" in the cloud.  ...  The Deep Learning machines for AI would be the new driver for the semiconductor industry.  ...  is best suited for training and deep learning in AI.  ... 
doi:10.1117/12.2504658 fatcat:i263hrl2k5fqfmnvlsswl6w3aa
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