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Checkpointing for Virtual Platforms and SystemC-TLM

Màrius Monton, Jakob Engblom, Mark Burton
2013 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Figure 3 . 1 : 31 Block Diagram (SystemC blocks grayed)Checkpointing for Virtual Platforms and SystemC-TLM-2 Figure 3 . 2 : 32 QEMU -SystemC DataflowVirtual Platforms and SystemC 61 Figure 3 . 3 :  ...  We introduce in deep detail the problem of checkpointing for Virtual Platforms, and the use of SystemC on Virtual Platforms. ➢ Chapter 3 Virtual Platforms and SystemC presents the methodology used to add  ... 
doi:10.1109/tvlsi.2011.2181881 fatcat:xhlbdcuu2ng7rpj5msizqzitaa

Fast Virtual Prototyping for Embedded Computing Systems Design and Exploration

Amir Charif, Gabriel Busnot, Rania Mameesh, Tanguy Sassolas, Nicolas Ventroux
2019 Proceedings of the Rapid Simulation and Performance Evaluation: Methods and Tools on - RAPIDO '19  
Virtual Prototyping has been widely adopted as a costeffective solution for early hardware and software co-validation.  ...  It introduces novel methods to leverage the QEMU dynamic binary translator and the abstraction levels offered by SystemC/TLM 2.0 to provide the best possible trade-offs between accuracy and performance  ...  An OVP model can be wrapped for inclusion in a SystemC model using TLM 2.0 interfaces.  ... 
doi:10.1145/3300189.3300192 dblp:conf/rapido/CharifBMSV19 fatcat:lelj2bs2undbngzgwueayul6qq

Checkpoint and Restore for SystemC Models [chapter]

Màrius Monton, Jakob Engblom, Christian Schröder, Jordi Carrabina, Mark Burton
2010 Lecture Notes in Electrical Engineering  
As a result, virtual platforms and platform components written in SystemC can be made more useful to software developers, and support smarter workflows. § Also PhD student at the Dpt.  ...  Save and Restore (or checkpointing) is a useful technique that can greatly assist target software and simulation model development and debug.  ...  Checkpointing is a key workflow enabler for systems and software development using a virtual platform.  ... 
doi:10.1007/978-90-481-9304-2_3 fatcat:ewzwn24l25ep5lojjsrhvivhre

On the Co-simulation of SystemC with QEMU and OVP Virtual Platforms [chapter]

Alessandro Lonardi, Graziano Pravadelli
2015 IFIP Advances in Information and Communication Technology  
On the contrary, no paper addresses integration between Open Virtual Platform (OVP) and SystemC.  ...  for integrating SystemC components with both QEMU and OVP.  ...  The authors would like to thank Filippo Cucchetto and Stefano Angeleri for their contribution in applying the proposed architecture to the case study reported in experimental results.  ... 
doi:10.1007/978-3-319-25279-7_7 fatcat:5xjd723ndnfmtmrlndlap5zb4a

Standard-compliant Parallel SystemC simulation of Loosely-Timed Transaction Level Models

Gabriel Busnot, Tanguy Sassolas, Nicolas Ventroux, Matthieu Moy
2020 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)  
To face the growing complexity of System-on-Chips (SoCs) and their tight time-tomarket constraints, Virtual Prototyping (VP) tools based on SystemC/TLM must get faster while keeping accuracy.  ...  By coupling a parallel SystemC kernel and memory access monitoring, we are able to keep SystemC atomic thread evaluation while leveraging the available host cores.  ...  We are interested in the Transaction-Level Modeling (TLM) [2] standard for SystemC which enables higher level of abstractions for faster simulation, increased interoperability and model reuse.  ... 
doi:10.1109/asp-dac47756.2020.9045568 dblp:conf/aspdac/BusnotSVM20 fatcat:z6ucyqgoonclvaopeieifcypbu

HdSC

Bruno Prado, Edna Barros, Thiago Figueiredo, André Aziz
2011 Proceedings of the 24th symposium on Integrated circuits and systems design - SBCCI '11  
Experimental results show that the virtual platform specified using this proposed approach can perform faster (up to 760x speed up) and high accurate (up to 12%) software simulation on native host environment  ...  This ISS model would be required only for performance and accuracy comparison purposes.  ...  ACKNOWLEDGEMENTS We would like to acknowledge the Ministry of Science, Technology and Innovation (MCTI) for the financial support provided by the funding agencies CNPq and CAPES.  ... 
doi:10.1145/2020876.2020917 dblp:conf/sbcci/PradoBFA11 fatcat:mqskqzqynzeyrcjyhulgb7bj5y

HdSC: A Fast and Preemptive Modeling for on Host HdS Development

Bruno Prado, Edna Barros, Thiago Figueredo, André Aziz
2012 Journal of Integrated Circuits and Systems  
Experimental results show that the virtual platform specified using this proposed approach can perform faster (up to 760x speed up) and high accurate (up to 12%) software simulation on native host environment  ...  This ISS model would be required only for performance and accuracy comparison purposes.  ...  ACKNOWLEDGEMENTS We would like to acknowledge the Ministry of Science, Technology and Innovation (MCTI) for the financial support provided by the funding agencies CNPq and CAPES.  ... 
doi:10.29292/jics.v7i1.356 fatcat:pzwy6ra2kvhijipmxdan7mizei

Design, synthesis and verification of a smart imaging core using SystemC

Wido Kruijtzer, Victor Reyes, Winfried Gehrke
2005 Design automation for embedded systems  
Furthermore, the use of SystemC TLM supports the integration of fast functional models of the coprocessors on a virtual prototype platform of the target architecture.  ...  The two coprocessors are successfully modeled and refined from C/C++-based algorithmic descriptions down to architecture reference models using SystemC and TLM concepts.  ...  Ghiath Alkadi from Philips Research Eindhoven for their contributions to the development of the smart imaging core.  ... 
doi:10.1007/s10617-006-0069-7 fatcat:77ro2kkrdfcgxf4hjf76ppq6cu

Modeling Power Consumption and Temperature in TLM Models

Matthieu Moy, Claude Helmstetter, Tayeb Bouhadiba, Florence Maraninchi
2015 Leibniz Transactions on Embedded Systems  
For this task, the application can be ignored or at least abstracted by some high level scenarios; at this stage, the actual embedded software is generally not available yet.  ...  Many techniques and tools exist to estimate the power consumption and the temperature map of a chip.  ...  Modeling Power Consumption and Temperature in TLM Models Power-Aware Software Execution on a Virtual Prototype To validate these power and thermal managers early in the design flow, one needs virtual  ... 
doi:10.4230/lites-v003-i001-a003 dblp:journals/lites/MoyHBM16 fatcat:g3qp5pfvgngknmglisrkcn7sdm

UNISIM: An Open Simulation Environment and Library for Complex Architecture Design and Collaborative Development

D. August, J. Chang, S. Girbal, D. Gracia-Perez, G. Mouchard, D. Penry, O. Temam, N. Vachharajani
2007 IEEE computer architecture letters  
Simulator development is already a huge burden for many academic and industry research groups; future complex or heterogeneous multi-cores, as well as the multiplicity of performance metrics and required  ...  an open library/repository for providing a consistent set of simulator modules.  ...  While SystemC provides some support for TLM simulators, neither LSE nor Asim do so. UNISIM augments TLM in two ways.  ... 
doi:10.1109/l-ca.2007.12 fatcat:h2qcbzazqfdbzmn6rue4kbbvku

The gem5 Simulator: Version 20.0+ [article]

Jason Lowe-Power, Abdul Mutaal Ahmad, Ayaz Akram, Mohammad Alian, Rico Amslinger, Matteo Andreozzi, Adrià Armejach, Nils Asmussen, Brad Beckmann, Srikant Bharadwaj, Gabe Black, Gedare Bloom (+66 others)
2020 arXiv   pre-print
for multiple architectures including x86, Arm, and RISC-V.  ...  The open-source and community-supported gem5 simulator is one of the most popular tools for computer architecture research.  ...  ACKNOWLEDGEMENTS The development of gem5 is community-driven and distributed.  ... 
arXiv:2007.03152v2 fatcat:jsz5yhipxrfypg5yhhbwpb5sc4

Ctherm: An Integrated Framework for Thermal-Functional Co-simulation of Systems-on-Chip

Sumeet S. Kumar, Amir Zjajo, Rene van Leuken
2015 2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing  
This paper presents Ctherm, an integrated framework for cycle-accurate thermal and functional evaluation of systems-on-chip.  ...  integrated co-simulation platform with an embedded thermal simulator.  ...  The authors would like to thank Michel Berkelaar for his inputs on floorplan generation for cache memories, and Jurrien de Klerk for his assistance with the instruction energy estimation.  ... 
doi:10.1109/pdp.2015.56 dblp:conf/pdp/KumarZL15 fatcat:gmtwg32lhnds5j4vd5ht7awtw4

Result-Oriented Modeling—A Novel Technique for Fast and Accurate TLM

Gunar Schirner, Rainer Domer
2007 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
For both bus systems, ROM achieves 100% accuracy and highest speeds. In essence, ROM eliminates the TLM tradeoff for a wide range of platforms.  ...  It frees the system designer from having multiple models for different purposes and extends the TLM idea to applications that require timing accurate simulation, such as real-time communication.  ...  Scope of This Work In this paper, we introduce a novel modeling technique for TLM, called result-oriented modeling (ROM), which eliminates this TLM tradeoff for a wide range of platforms.  ... 
doi:10.1109/tcad.2007.895757 fatcat:oq53bskjhbejnc26uh6uup3ima

Multi-level Latency Evaluation with an MDE Approach

Daniela Genius, Letitia W. Li, Ludovic Apvrille, Tullio Tanzi
2018 Proceedings of the 6th International Conference on Model-Driven Engineering and Software Development  
Designing embedded systems includes two main phases: (i) HW/SW Partitioning performed from high-level functional and architecture models, and (ii) Software Design performed with significantly more detailed  ...  Genius, D., Li, L., Apvrille, L. and Tanzi, T. Multi-level Latency Evaluation with an MDE Approach.  ...  However, simulations under SystemC are performed only at the quite high TLM-2.0 abstraction level (OSCI, 2008) which makes latency measurements less precise.  ... 
doi:10.5220/0006535902950302 dblp:conf/modelsward/GeniusLAT18 fatcat:oyjifn3novg3ritfxxhpurosbq

OCCN: a NoC modeling framework for design exploration

Marcello Coppola, Stephane Curaba, Miltos D. Grammatikakis, Riccardo Locatelli, Giuseppe Maruccia, Francesco Papariello
2004 Journal of systems architecture  
This API provides a new design pattern that enables creation and reuse of executable transaction level models ( TLMs) across a variety of SystemC-based environments and simulation platforms.  ...  Models are usually based on core functionality written in ANSI C and a SystemC-based wrapper.  ...  A model is a concrete representation of functionality for a target SoC. In contrast to component models, virtual SoC prototype (or virtual platform) refers to modeling the overall SoC.  ... 
doi:10.1016/j.sysarc.2003.07.002 fatcat:6vh6vhufubc65he3sekmjjinfq
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