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OPAL: A multi-layer hybrid photonic NoC for 3D ICs

Sudeep Pasricha, Shirish Bahirat
2011 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)  
Three-dimensional integrated circuits (3D ICs) offer a significant opportunity to enhance the performance of emerging chip multiprocessors (CMPs) using high density stacked device integration and shorter  ...  In this paper we propose and explore a novel multi-layer hybrid photonic NoC fabric (OPAL) for 3D ICs.  ...  To explore the impact of using OPAL in CMPs, we modeled OPAL by extensively modifying our in-house cycle accurate SystemC-based NoC simulator.  ... 
doi:10.1109/aspdac.2011.5722211 dblp:conf/aspdac/PasrichaB11 fatcat:6zy5jclmibf7hjb3plqapbttz4

On-Chip Network-Enabled Multicore Platforms Targeting Maximum Likelihood Phylogeny Reconstruction

T. Majumder, M. E. Borgens, P. P. Pande, A. Kalyanaraman
2012 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In this paper, we explore the design and performance evaluation of 2-D and 3-D NoC architectures for RAxML, which is one of the most widely used ML software suites.  ...  Simulations show that through appropriate choice of NoC architecture, and novel core design, allocation and placement strategies, our NoC-based implementation can achieve individual function-level speedups  ...  Roalson for the insightful discussions and comments that helped us better our understanding of the problem from a biological perspective.  ... 
doi:10.1109/tcad.2012.2188401 fatcat:h3bb5yjxnndqdh3wqjcog6hyty

A Framework for TSV Serialization-aware Synthesis of Application Specific 3D Networks-on-Chip

Sudeep Pasricha
2012 2012 25th International Conference on VLSI Design  
In this paper we propose a novel framework (MORPHEUS) for the synthesis of application-specific 3D networks on chip (NoCs).  ...  Comparisons with a previous work on application-specific 3D NoC synthesis also show improvements in power dissipation (up to 1.9×) and average latency (up to 1.6×).  ...  Every core is initially allocated a router that is later merged using a greedy heuristic. However, the method used for router and TSV allocation in layers is not clearly specified.  ... 
doi:10.1109/vlsid.2012.82 dblp:conf/vlsid/Pasricha12 fatcat:q5cchl4vlbgb7mtksmgjmxtfdy

Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3D Small-world Network-on-Chip [article]

Sourav Das, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty
2016 arXiv   pre-print
in a 3D IC.  ...  We demonstrate that a small-world network-based 3D NoC (3D SWNoC) performs significantly better than its 3D MESH-based counterparts.  ...  The NoC simulator uses wormhole routing, where the data flits follow the header flits once the router establishes a path. For regular 3D meshbased NoC, XYZ-dimension order based routing is used.  ... 
arXiv:1608.06972v1 fatcat:53ok6rx235honlq635qwkv7jii

On-Chip Communication Network for Efficient Training of Deep Convolutional Networks on Heterogeneous Manycore Systems

Wonje Choi, Karthi Duraisamy, Ryan Gary Kim, Janardhan Rao Doppa, Partha Pratim Pande, Diana Marculescu, Radu Marculescu
2018 IEEE transactions on computers  
The proposed NoC achieves 1.8x reduction in network latency and improves the network throughput by a factor of 2.2 for training CNNs, when compared to a highly-optimized wireline mesh NoC.  ...  By leveraging this knowledge, we design a hybrid Network-on-Chip (NoC) architecture, which consists of both wireline and wireless links, to improve the performance of CPU-GPU based heterogeneous manycore  ...  For instance, a massively parallelized CMP platform incorporating a customized NoC architecture was used to implement spiking neural networks [23] .  ... 
doi:10.1109/tc.2017.2777863 fatcat:actbfs64dbgsdct3tr4ubfqfjq

Nano-Photonic Networks-on-Chip for Future Chip Multiprocessors [chapter]

Cheng Li, Paul V. Gratz, Samuel Palermo
2015 More than Moore Technologies for Next Generation Computer Design  
in CMPs.  ...  We show in a 64-node implementation that LumiNOC enjoys 50% lower latency at low loads and ∼40% higher throughput per Watt on synthetic traffic versus previous PNoCs.  ...  Conventional NoCs in CMPs use wide, point-to-point electrical links to relay cache-lines between private mid-level and shared last-level processor caches [1] .  ... 
doi:10.1007/978-1-4939-2163-8_7 fatcat:a46olb47unbxrgov5rcknn7sly

Wormhole cut-through switching: Flit-level messages interleaving for virtual-channelless network-on-chip

Faizal Arya Samman, Thomas Hollstein, Manfred Glesner
2011 Microprocessors and microsystems  
A VLSI microrchitecture of a network-on-chip (NoC) router with a wormhole cut-through switching method is presented in this paper.  ...  The concept, on-chip microarchitecture, performance characteristics and interesting transient behaviors of the proposed NoC router that uses the wormhole cut-through switching method are presented in this  ...  reviewers, and DAAD (Deutcher Akademischer Austausch-Dienst, German Academic Exchange Service) awarding DAAD-Scholarship for Faizal Arya Samman to pursue doctoral degree at Darmstadt University of Technology in  ... 
doi:10.1016/j.micpro.2011.01.003 fatcat:j6nhztnl2vcj5e2vgofsijamja

Three-dimensional Integrated Circuits: Design, EDA, and Architecture

Guangyu Sun
2011 Foundations and Trends® in Electronic Design Automation  
In this article, we first give a brief introduction on the 3D integration technology, and then review the EDA challenges and solutions that can enable the adoption of 3D ICs, and finally present design  ...  using CMOS technology.  ...  Adding a large number of vertical links in a 3D crossbar to increase NoC connectivity results in increased path diversity.  ... 
doi:10.1561/1000000016 fatcat:usmthkco4rfavmnlvvmmgxolcq

High Performance Network-on-Chips (NoCs) Design: Performance Modeling, Routing Algorithm and Architecture Optimization [article]

Zhiliang Qian
2014 arXiv   pre-print
Finally, in the architecture level, we propose two new NoC structures using bi-directional links for the performance optimization.  ...  In this thesis, we have explored the high performance NoC design for MPSoC and CMP structures from the performance modeling in the offline design phase to the routing algorithm and NoC architecture optimization  ...  As shown in Fig. 1 Teraflops processor [16] which is a homogeneous NoC-based CMP platform and delivers up to 1.28 TFlops of performance.  ... 
arXiv:1406.3790v1 fatcat:rtr5v3ptu5f37eh3wwxfjusoom

Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs

Waqar Amin, Fawad Hussain, Sheraz Anjum, Sarzamin Khan, Naveed Khan Baloch, Zulqar Nain, Sung Won Kim
2020 IEEE Access  
Moreover, the best technique identified in each category based on the evaluation of performance results. INDEX TERMS Network-on-Chip, application mapping, NoC design, VOPD, System-on-Chip.  ...  Network-on-chip (NoC) is evolving as a better substitute for incorporating a large number of cores on a single system-on-chip (SoC).  ...  Instead of using classical queuing theory SVR-NoC uses a kernel-based support vector regression method to predict the channel average waiting time and the traffic flow latency.  ... 
doi:10.1109/access.2020.2982675 fatcat:kn6mkit3uvguvc2w6lx5dgddoe

Networks-on-chip in emerging interconnect paradigms: Advantages and challenges

Luca P. Carloni, Partha Pande, Yuan Xie
2009 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip  
Networks-on-chip (NoCs) have been proposed as a promising solution to simplify and optimize SoC design.  ...  Communication plays a crucial role in the design and performance of multi-core systems-on-chip (SoCs).  ...  Adding a large number of vertical links in a 3D crossbar to increase NoC connectivity results in increased path diversity.  ... 
doi:10.1109/nocs.2009.5071456 dblp:conf/nocs/CarloniPX09 fatcat:yrli36qr45fopjvu2lf5vuecuy

A NoC-based hybrid message-passing/shared-memory approach to CMP design

Mario R. Casu, Massimo Ruo Roch, Sergio V. Tota, Maurizio Zamboni
2011 Microprocessors and microsystems  
A NoC-based hybrid message-passing/shared-memory approach to CMP design / Casu M.R.; Ruo Roch M.; Tota S.; Zamboni M.  ...  We developed a fast SystemC based cycle-accurate simulator for design space explorations that we used to evaluate the performance with real benchmarks.  ...  Acknowledgments The authors wish to thank Luca Rostagno for his help with SystemC simulations, and Simone Bonsignore who helped develop the RTL version of the NoC interface.  ... 
doi:10.1016/j.micpro.2010.09.006 fatcat:dq5oxbatnfdhxm2w6lgw3tarse

Estimation of Optimized Energy and Latency Constraint for Task Allocation in 3d Network on Chip

Vaibhav Jha, Mohit Jha, G K Sharma
2014 International Journal of Computer Science & Information Technology (IJCSIT)  
In this paper we test the pre-existing proposed algorithms and introduced a new energy skilled algorithm for 3D NoC architecture.  ...  Cluster based approach is mapped onto NoC using Dynamic Diagonal Mapping (DDMap), Crinkle and Spiral algorithms and found DDmap provides improved result.  ...  In this paper, a heuristic OS-level technique is proposed that performs thermal-aware task scheduling on a 3D chip multiprocessor (CMP).  ... 
doi:10.5121/ijcsit.2014.6205 fatcat:2j6i7qqqxjcc7emytdtlv4zgqe

A Survey of Machine Learning Applied to Computer Architecture Design [article]

Drew D. Penney, Lizhong Chen
2019 arXiv   pre-print
Machine learning has enabled significant benefits in diverse fields, but, with a few exceptions, has had limited impact on computer architecture.  ...  The paper further analyzes current practice to highlight useful design strategies and identify areas for future work, based on optimized implementation strategies, opportune extensions to existing work  ...  [60] used a ML-based ST AGE algorithm to efficiently explore small-world inspired 3D NoC designs.  ... 
arXiv:1909.12373v1 fatcat:o4nscgkjfbes7kqwmtjvvgl3oa

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

Prateek Shantharama, Akhilesh S. Thyagaturu, Martin Reisslein
2020 IEEE Access  
[258] have proposed a Multiple Ring-based Optical NoC (MRONoC) design which uses ring based routing, as well as redundant paths to re-use the wavelength resources without contentions.  ...  Typically, the use of an 3D NoC is asymmetric due to uneven scheduling of computing tasks, leading to uneven aging of the 3D NoC, as illustrated in Fig. 32 .  ... 
doi:10.1109/access.2020.3008250 fatcat:kv4znpypqbatfk2m3lpzvzb2nu
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