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Characterization and Improvement of Time-Memory Trade-Off Based on Perfect Tables

Gildas Avoine, Pascal Junod, Philippe Oechslin
2008 ACM Transactions on Privacy and Security  
We fill this lack by analyzing the perfect form of classic tables, distinguished point-based tables, and rainbow tables.  ...  Cryptanalytic time-memory trade-offs have been studied for twenty five years and have benefited from several improvements since the original work of Hellman.  ...  For large memories and small gains in time the trade-off can be implemented with one single perfect table. In that case the trade-off relation becomes T ≈ N/M .  ... 
doi:10.1145/1380564.1380565 fatcat:tmo3dvtinrd2bbkuhmrapolgxm

Time-Memory Trade-Offs: False Alarm Detection Using Checkpoints [chapter]

Gildas Avoine, Pascal Junod, Philippe Oechslin
2005 Lecture Notes in Computer Science  
In this paper, we also present theoretical analysis of time-memory trade-offs, and give a complete characterization of the variant based on rainbow tables.  ...  Since the original publication of Martin Hellman's cryptanalytic time-memory trade-off, a few improvements on the method have been suggested.  ...  In such a commercial application, time is money, and therefore any improvement of time-memory trade-off also. In Section 2, we give a rough idea of our technique based on checkpoints.  ... 
doi:10.1007/11596219_15 fatcat:ozcrrb7zgvb2vpupshsc62bxsm

Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers

Davide Bertozzi, Stefano Di Carlo, Salvatore Galfano, Marco Indaco, Piero Olivo, Paolo Prinetto, Cristian Zambelli
2015 ACM Transactions on Embedded Computing Systems  
Designing NAND flash based systems based on worst-case scenarios leads to waste of resources in terms of performance, power consumption, and storage capacity.  ...  There is a clear trend toward supporting differentiated access modes in flash memory controllers, each one setting a differentiated trade-off point in the performance-reliability optimization space.  ...  BCH codes are therefore a perfect choice for correcting errors in these devices. The construction of a BCH code is based on Galois field GF(2 m ).  ... 
doi:10.1145/2629562 fatcat:2msykxn35ne4phtmnw7f3mnjma

Bridging the Processor-Memory Performance Gapwith 3D IC Technology

C.C. Liu, I. Ganusov, M. Burtscher, S. Tiwari
2005 IEEE Design & Test of Computers  
Memory access times, however, have improved by less than 10% per year. 1 The resulting gap between logic and memory performance has forced microprocessor designs toward complex and power-hungry architectures  ...  This article examines how 3D IC technology can improve interactions between the processor and memory.  ...  We are indebted to the following people for many invaluable discussions: John Barth, Norman Jouppi, Rajit Manohar, and Richard Matick, with special thanks to Sally McKee and David Wang.  ... 
doi:10.1109/mdt.2005.134 fatcat:aarbm2vy7rg6jnqzb6mz3e3hia

Joint Power Management and Adaptive Modulation and Coding for Wireless Communications Systems With Unreliable Buffering Memories

Muhammad S. Khairy, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi
2014 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
Based on this model, different AMC and power management algorithms are presented that utilize the received SNR estimates to find the best AMC mode and memory voltage that achieves performance goals at  ...  This paper investigates the interaction between on-chip power management via VoS on embedded memories versus network based AMC techniques.  ...  Table I shows the buffering memory voltage states, the corresponding error rate in the memory and the normalized power consumption based on 6T SRAM in 65 nm process technology [21] .  ... 
doi:10.1109/tcsi.2014.2309791 fatcat:6k7hpjlfqnei7krgg6vmjwwrsy

Stereo for robots: Quantitative evaluation of efficient and low-memory dense stereo algorithms

Federico Tombari, Stefano Mattoccia, Luigi Di Stefano
2010 2010 11th International Conference on Control Automation Robotics & Vision  
The evaluation is performed on a standard benchmark dataset as well as on a novel dataset, acquired by means of an active technique, characterized by realistic working conditions.  ...  Despite the significant number of stereo vision algorithms proposed in literature in the last decade, most proposals are notably computationally demanding and/or memory hungry so that it is unfeasible  ...  Instead, approaches based on Scanline Optimization (SO) and Dynamic Programming (DP) trade off accuracy for efficiency by minimizing a global energy term over image scanlines.  ... 
doi:10.1109/icarcv.2010.5707826 dblp:conf/icarcv/TombariMS10 fatcat:fayymr3qonactfhzrfnkft4ktq

Flash memory efficient LTL model checking

S. Edelkamp, D. Sulewski, J. Barnat, L. Brim, P. Šimeček
2011 Science of Computer Programming  
For flash memory efficient off-line LTL model checking, which aims at generating a minimal counterexample and scans the entire state space at least once, we analyze the effect of outsourcing a memory-based  ...  perfect hash function from RAM to flash memory.  ...  Acknowledgements We would like to thank Martin Dietzfelbinger for his help to derive the lower bound on perfect hashing, Peter Kissmann for his rigorous proof reading, and the anonymous reviewers for the  ... 
doi:10.1016/j.scico.2010.03.005 fatcat:5kkssybrs5dibhqgwyhvsv3xfi

Exploring compromises among timing, power and temperature in three-dimensional integrated circuits

Hao Hua, Chris Mineo, Kory Schoenfliess, Ambarish Sule, Samson Melamed, Ravi Jenkal, W. Rhett Davis
2006 Proceedings of the 43rd annual conference on Design automation - DAC '06  
In order to help understand this trade-off, physical design experiments were performed on a low-power and a high-performance design in an existing 3DIC technology.  ...  These results show a reduction in energy and delay of up to 27% and 20% compared to a traditional 2DIC approach.  ...  Lastly, thanks to James Stine at the Illinois Institute of Technology for generously providing access to the IIT-SoC standard-cell characterization scripts.  ... 
doi:10.1145/1146909.1147161 dblp:conf/dac/HuaMSSMJD06 fatcat:n5b5v7rxtzajtlo7gsc4ywyr6i

Exploring compromises among timing, power and temperature in three-dimensional integrated circuits

Hao Hua, C. Mineo, K. Schoenfliess, A. Sule, S. Melamed, R. Jenkal, W.R. Davis
2006 Proceedings - Design Automation Conference  
In order to help understand this trade-off, physical design experiments were performed on a low-power and a high-performance design in an existing 3DIC technology.  ...  These results show a reduction in energy and delay of up to 27% and 20% compared to a traditional 2DIC approach.  ...  Lastly, thanks to James Stine at the Illinois Institute of Technology for generously providing access to the IIT-SoC standard-cell characterization scripts.  ... 
doi:10.1109/dac.2006.229427 fatcat:yfjokkkk6zddpcbydm3uvzwoum

Coordinated Management of Processor Configuration and Cache Partitioning to Optimize Energy under QoS Constraints [article]

Mehrzad Nejat, Madhavan Manivannan, Miquel Pericas, Per Stenstrom
2019 arXiv   pre-print
A first contribution is a systematic study of the resource trade-offs enabled when trading between the three classes of resources in a coordinated fashion.  ...  Overall, we show that up to 18% of energy, and on average 10%, can be saved using the proposed scheme.  ...  This is based on the observation that MLP has a strong influence on the trade-offs between core configuration and LLC partitioning.  ... 
arXiv:1911.05114v1 fatcat:ino66ycytjhwpk6jfrc5vsp4nu

Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology

Daniele Ludovici, Georgi N. Gaydadjiev, Francisco Gilabert, Maria E. Gomez, Davide Bertozzi
2010 Proceedings of the Third International Workshop on Network on Chip Architectures - NoCArc '10  
To ease such a choice, the networking literature offers a plethora of works about topology analysis and characterization for the off-chip domain.  ...  Nowadays, system designers have adopted Networks-on-Chip as communication infrastructure of general-purpose tile-based Multi-Processor System-on-Chip (MPSoC).  ...  When extending the analysis to larger 64-tile networks, the unaffordable time and memory requirements for the synthesis of such systems makes a comprehensive exploration based on postlayout figures unfeasible  ... 
doi:10.1145/1921249.1921259 dblp:conf/micro/LudoviciGVGB10 fatcat:xdpsu2mqi5gahgir43c4za5suq

Predicting Coherence Communication by Tracking Synchronization Points at Run Time

Socrates Demetriades, Sangyeun Cho
2012 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture  
Based on this observation, we build a predictor that can improve the miss latency of a directory protocol by 13%.  ...  Predicting target processors that a coherence request must be delivered to can improve the miss handling latency in shared memory systems.  ...  Milos Prvulovic, members of Pitt's XCG (formerly CAST) group, and the anonymous reviewers for their constructive comments and suggestions.  ... 
doi:10.1109/micro.2012.40 dblp:conf/micro/DemetriadesC12 fatcat:uytjuogdargh7hlttq7hstnyki

Staged simulation

Kevin Walsh, Emin Gün Sirer
2004 ACM Transactions on Modeling and Computer Simulation  
We present a general and flexible framework for staging, and identify the advantages and trade-offs of its application to wireless network simulations, a particularly challenging simulation domain.  ...  For instance, time-shifting events to access memory sequentially instead of randomly can speed up execution by taking advantage of memory caching and prefetching.  ...  Memory Utilization and Performance Staging is based on a fundamental trade-off between caching and reuse in memory versus recomputation at the CPU.  ... 
doi:10.1145/985793.985797 fatcat:4qd56muqvzdprpmothbzm2ncp4

Designing a modern memory hierarchy with hardware prefetching

Wei-Fen Lin, S.K. Reinhardt, D. Burger
2001 IEEE transactions on computers  
With eight Rambus channels, these 10 benchmarks improve to within 10 percent of the performance of a perfect L2 cache.  ...  We show that, even with an aggressive, next-generation memory system using four Direct Rambus channels and an integrated onemegabyte level-two cache, a processor still spends over half its time stalling  ...  TRADE-OFFS IN EXPLOITING SPATIAL LOCALITY In this section, we examine the L2 cache and memory channel organization, exploring the trade-offs between spatial locality and pollution versus bandwidth and  ... 
doi:10.1109/12.966495 fatcat:xsfr5snle5ho3liqmt3i7v2p24

Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS Amplification

Linkun Wu, David San Segundo Bello, Philippe Coppejans, Jan Craninckx, Andreas Süss, Maarten Rosmeulen, Piet Wambacq, Jonathan Borremans
2018 Sensors  
Focusing on the sampling noise, the system level trade-off of the proposed pixel architecture is discussed, showing its advantages on the noise, power, and scaling capability.  ...  A comprehensive noise model is developed for optimizing the trade-off between the area and noise.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/s18113683 fatcat:gfrtbeqaxrdonfyzri44vpqgym
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