Filters








11,539 Hits in 7.3 sec

Grand challenges: companies and universities working for a better society (Extended Abstracts)

MARTA UGOLINI
2021 Sinergie Italian Journal of Management  
Gli Extended Abstract racconti in questo volume affrontano la tematica con una varietà di argomenti, punti di vista, prospettive.  ...  ., SASSALOS, S. (2000), "A different voice in the boardroom: How the presence of women directors affects board influence over management", Global Focus, vol. 12, n. 2, pp. 13-22.  ...  are driven to care for the local natural and cultural environment in their interactions with the tourists.  ... 
doi:10.7433/srecp.ea.2020.01 fatcat:7tu5ulmovbauzc744x5nxjx2by

Integrating back, history and bookmarks in web browsers

Shaun Kaasten, Saul Greenberg
2001 CHI '01 extended abstracts on Human factors in computer systems - CHI '01  
With more extended use of recency Back, users may realize that the hub pages are accessible and may find the duplication of pages unnecessary.  ...  Implementing global history Implementing global history requires all of the browser windows to be aware of all navigations.  ... 
doi:10.1145/634288.634291 fatcat:fqvk5uiji5h47lohxdh6ntzsyi

Placement for large-scale floating-gate field-programable analog arrays

F. Baskaya, S. Reddy, Sung Kyu Lim, D.V. Anderson
2006 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Our goal in this paper is to develop the first placement algorithm for large-scale floating-gate-based FPAAs with a focus on the minimization of the parasitic effects on interconnects under various device-related  ...  Our FPAA placement algorithm then maps each cluster to a computational analog block (CAB) of the target FPAA while focusing on routing switch usage and balance again.  ...  Placement Algorithm Our FPAA placement consists of two steps: constructive placement and stochastic refinement.  ... 
doi:10.1109/tvlsi.2006.878477 fatcat:rbgc7paymnelli5itut5xf2xbq

A pseudo-hierarchical methodology for high performance microprocessor design

A. Bertolet, G. Rodgers, D. Willmott, T. Bairley, T. Decker, V. Girardi, Y. Lapid, M. Murphy, P. A. Scott, R. Weiss, K. Carpenter, K. Carrig (+6 others)
1997 Proceedings of the 1997 international symposium on Physical design - ISPD '97  
Critical aspects of the methodology include an integrated database for design control, algorithmic power grid generation, fully customized clock network insertion, timing driven placement and routing,  ...  This design flow consists of multiple iterations of placement, global routing, parasitic extraction, and timing analysis (Figure 4) .  ...  During abstract generation, the symbol and layout are examined for consistency.  ... 
doi:10.1145/267665.267702 dblp:conf/ispd/BertoletCCCDFKPPRWBDGLMSW97 fatcat:tyvdnud24fbxvohuufqn2o5tgm

BEAR-FP: A ROBUST FRAMEWORK FOR FLOORPLANNING

MASSOUD PEDRAM, ERNEST S. KUH
1992 International Journal of High Speed Electronics and Systems  
linear assignment and driven by the global routing solution and oorplan topology, and an e ective timing-driven oorplanning scheme are among the other novel features of the oorplanner.  ...  This paper presents a hierarchical oorplanning approach for macrocell layouts which is based on the bottom-up clustering, shape function computation, and top down oorplan optimization with integrated global  ...  and with timing-driven placement.  ... 
doi:10.1142/s0129156492000060 fatcat:rpjhsqwenbdalonkrmyfgjpujm

Reflective HCI

Paul Dourish, Janet Finlay, Phoebe Sengers, Peter Wright
2004 Extended abstracts of the 2004 conference on Human factors and computing systems - CHI '04  
In extending this work to the responsive media environment of the TGarden, the relation is not limited to the rhythm of one body with another, but of one body with the salient responsive elements in the  ...  ABSTRACT FIASCO is a location-based game that takes place on a website and on street corners.  ...  It has continued with the support of Ken Anderson of Intel Research. We also thank Paul Berry, who built the FIASCO back-end.  ... 
doi:10.1145/985921.986203 dblp:conf/chi/DourishFSW04 fatcat:2riaoweryzhnza25n4hwbghwha

Manufacturability Aware Routing in Nanometer VLSI

David Z. Pan
2010 Foundations and Trends® in Electronic Design Automation  
The challenge with model-based approach is how to abstract a set of reasonably accurate and high-fidelity models at various abstraction levels to guide physical layout optimizations.  ...  The entire chip area is further dissected into global routing grid in order to reduce routing complexity as shown in Fig. 1 . 1 11 Illustration of a modern routing system which consists of three routing  ... 
doi:10.1561/1000000015 fatcat:ytvthtu4b5hwzdume5ffs4yxpe

Design and implementation of a single system image operating system for ad hoc networks

Hongzhou Liu, Tom Roeder, Kevin Walsh, Rimon Barr, Emin Gün Sirer
2005 Proceedings of the 3rd international conference on Mobile systems, applications, and services - MobiSys '05  
MagnetOS meets these goals by making the entire network operate as an extended Java virtual machine.  ...  MagnetOS applications are comprised of event handlers that communicate with each other by raising well-typed events.  ...  Publish-Subscribe Our second application consists of a basic publishsubscribe system. The application provides a channel abstraction to which clients can subscribe and publish.  ... 
doi:10.1145/1067170.1067187 dblp:conf/mobisys/LiuRWBS05 fatcat:louevdu2abfynipeepflrjt63i

FPGA-SPICE: A simulation-based power estimation framework for FPGAs

Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2015 2015 33rd IEEE International Conference on Computer Design (ICCD)  
Experimental results show that the global routing architecture consumes 50% of the total power, the local routing architecture claims for 40% of the total power, and the remaining 10% comes from the LUTs  ...  Full-chiplevel testbenches dump the netlists associated with the complete FPGA fabric.  ...  A length-L channel wire is abstracted as L cascaded segments, each of which spans a unique CLB. Fig. 7 (a) depicts a length-2 channel wire in unidirectional routing architecture [6] .  ... 
doi:10.1109/iccd.2015.7357183 dblp:conf/iccd/TangGM15 fatcat:53xm2rjlunef5lp2eghtcvobry

Towards an adaptive execution of applications in heterogeneous embedded networks

Andreas Scholz, Stephan Sommer, Alfons Kemper, Alois Knoll, Christian Buckl, Gerd Kainz, Jörg Heuer, Anton Schmitt
2010 Proceedings of the 2010 ICSE Workshop on Software Engineering for Sensor Network Applications - SESENA '10  
The nodes contained in these networks can differ greatly w.r.t. their storage, processing and sensing/acting capabilities, ranging from very simple sensor devices with very limited resources over programmable  ...  In this paper, we will present a model driven development approach that allows the specification of application requirements, and a corresponding middleware solution that supports the automatic adaptation  ...  the data with costs 8 (stream with data rate 4 routed over 2 links).  ... 
doi:10.1145/1809111.1809120 dblp:conf/icse/ScholzSKKBKHS10 fatcat:y5r22eglqjexfhuw3rkopk6ase

DFuse

Rajnish Kumar, Matthew Wolenetz, Bikash Agarwalla, JunSuk Shin, Phillip Hutto, Arnab Paul, Umakishore Ramachandran
2003 Proceedings of the first international conference on Embedded networked sensor systems - SenSys '03  
It consists of a data fusion API and a distributed algorithm for energy-aware role assignment.  ...  We extend these techniques to future sensor networks and ask two related questions: (a) what is the appropriate set of data fusion techniques, and (b) how do we dynamically assign aggregation roles to  ...  A fusion channel is a named, global entity that abstracts a set of inputs and encapsulates a programmer-supplied fusion function.  ... 
doi:10.1145/958503.958505 fatcat:taxp5lujjrbahfvsgiu5ym6qty

DFuse

Rajnish Kumar, Matthew Wolenetz, Bikash Agarwalla, JunSuk Shin, Phillip Hutto, Arnab Paul, Umakishore Ramachandran
2003 Proceedings of the first international conference on Embedded networked sensor systems - SenSys '03  
It consists of a data fusion API and a distributed algorithm for energy-aware role assignment.  ...  We extend these techniques to future sensor networks and ask two related questions: (a) what is the appropriate set of data fusion techniques, and (b) how do we dynamically assign aggregation roles to  ...  A fusion channel is a named, global entity that abstracts a set of inputs and encapsulates a programmer-supplied fusion function.  ... 
doi:10.1145/958491.958505 dblp:conf/sensys/KumarWASHPR03 fatcat:ds5z7mhww5emtpcticc5vyps5i

Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis

Michael A. Riepe, Karem A. Sakallah
1999 Proceedings of the 1999 international symposium on Physical design - ISPD '99  
Circuits designed in these non-dual ratioed logic families can be highly irregular with complex geometry sharing and non-trivial routing.  ...  In this work we define the synthesis of complex 2-dimensional digital cells as a new problem which we call transistor-level micro-placement and routing.  ...  This approach enables chain optimization to proceed with detailed knowledge of the placement and global routing cost function.  ... 
doi:10.1145/299996.300028 dblp:conf/ispd/RiepeS99 fatcat:vvxc43byorgcvobd7jr7nmmd5m

Transistor placement for noncomplementary digital VLSI cell synthesis

Michael A. Riepe, Karem A. Sakallah
2003 ACM Transactions on Design Automation of Electronic Systems  
We combine our placement algorithms with third-party routing and compaction tools, and present the results of a series of experiments which compare our technique with a commercial cell synthesis tool.  ...  Circuits designed in these noncomplementary ratioed logic families can be highly irregular, with complex diffusion sharing and nontrivial routing.  ...  This late-binding technique allows chain optimization to proceed with detailed knowledge of the global placement and routing cost function. (3) A unique placement model in which the atomic placeable objects  ... 
doi:10.1145/606603.606608 fatcat:rnc3wsgs2jc3hmxi6jsbywth2e

Scalable and deterministic timing-driven parallel placement for FPGAs

Chris C. Wang, Guy G.F. Lemieux
2011 Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '11  
This thesis describes a parallel implementation of the timing-driven VPR 5.0 simulated-annealing placement engine.  ...  Specifically, at the point where the parallel placer begins to dominate over the serial placer, the post-routing minimum channel width, wirelength and critical-path delay degrades 13%, 10% and 7% respectively  ...  Figure 6 . 1 : 61 Runtime versus quality comparison for post routing minimum routable channel width, wirelength and critical-path delay Table of Contents of Abstract . . . . . . . . . . . . . . . . .  ... 
doi:10.1145/1950413.1950445 dblp:conf/fpga/WangL11 fatcat:2xpnc3uhebclvftblpwskizlru
« Previous Showing results 1 — 15 out of 11,539 results