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Prototype performance studies of a full mesh ATCA-based general purpose data processing board

2013 2013 IEEE Nuclear Science Symposium and Medical Imaging Conference (2013 NSS/MIC)  
to board communication channels while keeping the design as simple as possible.  ...  A custom Advanced Telecommunications Computing Architecture data processing board is designed with the goal of creating a scalable architecture abundant in flexible, non-blocking, high bandwidth board  ...  All GTX transceiver channels have been tested and characterized using the IBERT tool.  ... 
doi:10.1109/nssmic.2013.6829449 fatcat:up3c4gnxljfmxirjpcxeyzxq4m

Prototype performance studies of a Full Mesh ATCA-based General Purpose Data Processing Board [article]

Yasuyuki Okumura, Jamieson Olsen, Tiehui Ted Liu, Hang Yin
2014 arXiv   pre-print
to board communication channels while keeping the design as simple as possible.  ...  A custom Advanced Telecommunications Computing Architecture data processing board is designed with the goal of creating a scalable architecture abundant in flexible, non-blocking, high bandwidth board  ...  All GTX transceiver channels have been tested and characterized using the IBERT tool.  ... 
arXiv:1403.4331v1 fatcat:2tnfdo3k3ngzxfiiffcrsuujcu

Low-Power Direct Conversion Transceiver for 915 MHz Band IEEE 802.15.4b Standard Based on 0.18 μm CMOS Technology

Trung-Kien Nguyen, Viet-Hoang Le, Quoc-Hoang Duong, Seok-Kyun Han, Sang-Gug Lee, Nak-Seon Seong, Nae-Soo Kim, Cheol-Sig Pyo
2008 ETRI Journal  
Low power and low cost are achieved by optimizing the transceiver architecture and circuit design techniques.  ...  The proposed transceiver is implemented in a 0.18 μm CMOS process and occupies 10 mm 2 of silicon area.  ...  Transceiver Architecture Recently, direct conversion transceiver architecture has been adopted for many wireless transceiver implementations due to its high level of integration and low power consumption  ... 
doi:10.4218/etrij.08.0107.0034 fatcat:hcfocrhmord4jpecwt7253lpwm

Beyond 100 Gb/s: Capacity, Flexibility, and Network Optimization

Kim Roberts, Qunbi Zhuge, Inder Monga, Sebastien Gareau, Charles Laperle
2017 Journal of Optical Communications and Networking  
To achieve capacities of 400 Gb∕s and more, coherent transceivers will operate at higher symbol rates.  ...  At the network control and management level, new tools are being developed to achieve a more efficient utilization of networks.  ...  Further improvement to the FEC algorithm will be designed in the R-FEC to enable up to a 1 dB additional margin over the Q-FEC.  ... 
doi:10.1364/jocn.9.000c12 fatcat:vgvorw2jgbedlodg4xbpb3uj7e

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology

John F. Bulzacchelli, Mounir Meghelli, Sergey V. Rylov, Woogeun Rhee, Alexander V. Rylyakov, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Aichin Chung, Troy J. Beukema, Petar K. Pepeljugoski, Lei Shan (+3 others)
2006 IEEE Journal of Solid-State Circuits  
Operation at 10-Gb/s with good power efficiency is achieved by using half-rate architectures in both transmitter and receiver.  ...  This paper presents a 90-nm CMOS 10-Gb/s transceiver for chip-to-chip communications.  ...  As an indicator of operating margins at 10 Gb/s, Fig. 16 shows plots of the receiver bit-error rate (BER) as a function of data sampling time (often referred to as "bathtub curves").  ... 
doi:10.1109/jssc.2006.884342 fatcat:jdetfh6ngnh5deuti3uxpdxtx4

Audio streaming over low data rate wireless system

M. Radhika, Dr.K. Rama Naidu
2011 International Journal of Smart Sensor and Adhoc Network.  
Audio applications over wireless networks have recently emerged as a promising research field.  ...  However, the limits in terms of communication bandwidth and transmission power have withstood the design of low-power embedded nodes for audio communication.  ...  SX1231 transceiver datasheet referred from the reference [2] . II. FIRE SYSTEM ARCHITECTURE Figure1: Architecture of Fire system The Architecture of Fire system as shown in.Figure1.  ... 
doi:10.47893/ijssan.2011.1012 fatcat:ufub6lvd55buhndfeouig66d54

CMOS compatible many-core noc architectures with multi-channel millimeter-wave wireless links

Sujay Deb, Kevin Chang, Miralem Cosic, Amlan Ganguly, Partha P. Pande, Deukhyoun Heo, Benjamin Belzer
2012 Proceedings of the great lakes symposium on VLSI - GLSVLSI '12  
Multiple wireless shortcuts operating simultaneously provide an energy efficient solution for design of many-core communication infrastructures.  ...  Traditional many-core designs based on the Network-on-Chip (NoC) paradigm suffer from high latency and power dissipation as the system size scales up due to their inherent multi-hop communication.  ...  The transceiver area overhead for mWNoC is marginally higher than RFNoC and BWNoC.  ... 
doi:10.1145/2206781.2206822 dblp:conf/glvlsi/DebCCGPHB12 fatcat:trrqmmeslza4vhghzlzb4vk5oq

The FC7 AMC for generic DAQ & control applications in CMS

M. Pesaresi, M. Barros Marin, G. Hall, M. Hansen, G. Iles, A. Rose, F. Vasey, P. Vichoudis
2015 Journal of Instrumentation  
order to fine tune each channel to extract the widest possible operating margin.  ...  Left: bath-tub scans, using the Xilinx internal margin analysis tools, for the KC705 with FM-S18 FMC at 10 Gbps (PRBS-7, channels DP0-3), compared to the KC705 reference SFP operating in loopback.  ...  Performance tests indicate wide margins of operation on all channels and error free running with up to 10 14 bits transmitted per link.  ... 
doi:10.1088/1748-0221/10/03/c03036 fatcat:thf6wfqotvasjhygf43lk3xq5y

A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology

Huaide Wang, Jri Lee
2010 IEEE Journal of Solid-State Circuits  
Fabricated in 65-nm CMOS, the transceiver (excluding clock generating PLL and CDR circuits) delivers 21-Gb/s data (2 31 1 PRBS) over 40-cm FR4 channel while consuming 87 mW from a 1.2-V supply.  ...  The one-tap decision-feedback equalizer merges the summer and the slicer into the flipflop, shortening the feedback path and speeding up the operation considerably.  ...  Receiver Architecture C. DFE Design Conventional full-rate DFEs fail to operate at very high speed, since they suffer from inadequate settling time for the feedback signal.  ... 
doi:10.1109/jssc.2010.2040117 fatcat:2cwq2mtaijfxreo42f6bpaujie

QoT assessment of the optical spectrum as a service in disaggregated network scenarios

Kaida Kaeval, Tobias Fehenberger, Jim Zou, Sander Lars Jansen, Klaus Grobe, Helmut Griesser, Jörg-Peter Elbers, Marko Tikas, Gert Jervan
2021 Journal of Optical Communications and Networking  
configurations in order to maximize capacity and increase service margins in a low-margin operation regime.  ...  The potential to operate third-party terminals over multi-domain transparent optical networks attracts operators and customers to implement Optical Spectrum as a Service (OSaaS).  ...  We thank Tele2 Estonia for their continuous cooperation and help regarding the research on Optical Spectrum as a Service in Disaggregated Networks.  ... 
doi:10.1364/jocn.423530 fatcat:dexgrx424zhmvlzy2xhoqhvvrq

A Single-Chip CMOS-Based Parallel Optical Transceiver Capable of 240-Gb/s Bidirectional Data Rates

Clint L. Schow, Fuad E. Doany, Christian W. Baks, Young H. Kwark, Daniel M. Kuchta, Jeffrey A. Kash
2009 Journal of Lightwave Technology  
The transceiver measures 3.25 2 5.25 mm and consumes 2.15 W of power with all channels fully operational.  ...  The per-bit power consumption is as low as 9 mW/Gb/s, and this is the first single-chip optical transceiver capable of channel rates in excess of 10 Gb/s.  ...  ., in producing the circuit designs for the first phase of the project are also appreciated. The authors also would like to thank A. Rylyakov, P. Pepeljugoski, L. Schares, and M.  ... 
doi:10.1109/jlt.2008.927759 fatcat:7xrgj52eiraypl6zibytue5yla

Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges

Sujay Deb, Amlan Ganguly, Partha Pratim Pande, Benjamin Belzer, Deukhyoun Heo
2012 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
In this paper, we present various challenges and emerging solutions regarding the design of an efficient and reliable WiNoC architecture.  ...  This opens up new opportunities for detailed investigations into the design of wireless NoCs (WiNoCs) with on-chip antennas, suitable transceivers and routers.  ...  Due to limitations in the available bandwidth and complexity of transceiver designs, multiple nonoverlapping channels at high operating frequencies is a nonscalable solution.  ... 
doi:10.1109/jetcas.2012.2193835 fatcat:vbd2mj7os5h7faafy7eo6rive4

An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using Simultaneous Bi-Directional Dual (Base+RF)-Band Signaling

Gyung-Su Byun, Yanghyo Kim, Jongsun Kim, Sai-Wang Tam, Mau-Chung Frank Chang
2012 IEEE Journal of Solid-State Circuits  
The dual-band transceiver achieves error-free operation (BER 10 15 ) with 2 23 1 PRBS at 8.4 Gb/s over a distance of 10 cm.  ...  Incorporating both RF-band and baseband transceiver designs, this prototype demonstrates an energy-efficient and high-bandwidth solution for future mobile memory I/O interface.  ...  TRANSCEIVER CIRCUIT DESIGN A.  ... 
doi:10.1109/jssc.2011.2164709 fatcat:vyeewglkdzaohae5m6xvtgdkuq

Prototyping Processing-Demanding Physical Layer Systems Featuring Single Or Multi-Antenna Schemes

Nikolaos Bartzoudis, Oriol Font-Bach, David López Bueno, Antonio Pascual Iserte
2011 Zenodo  
Figure 2 is depicting the general architecture of the transceiver, containing as well various system-features and specifications (channel coding was not implemented).  ...  Figure 1 : 1 The design and implementation flow-chart. Figure 2 : 2 Overview of the MIMO transceiver architecture.  ... 
doi:10.5281/zenodo.42741 fatcat:aceip5e3d5dhnjfv3bj7h2im4a

A VHDL-AMS Simulation Environment for an UWB Impulse Radio Transceiver

M.R. Casu, M. Crepaldi, M. Graziano
2008 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
A few works document the use of VHDL-AMS as an effective tool for the efficient design of complex systems using a top-down methodology.  ...  Therefore, using VHDL-AMS as a common hardware description language for the whole UWB transceiver is the key for the development of a successful and efficient simulation tool. IV.  ...  Her research interests include the design of ultra-wide-band CMOS transceivers and the development of models and algorithms for the design of CMOS noise-tolerant digital and mixed-signal circuits.  ... 
doi:10.1109/tcsi.2008.916402 fatcat:dkrdub7rsbbmfpb4shzalpaxwe
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