Filters








942 Hits in 7.4 sec

Latch-Based Logic Locking [article]

Joseph Sweeney, Mohammed Zackriya V, Samuel Pagliarini, Lawrence Pileggi
2020 arXiv   pre-print
In this paper, we propose latch-based logic locking, which manipulates both the flow of data and logic in the design.  ...  Importantly, we show that the design overhead with this approach is significantly less than with previous logic locking schemes, while resisting model checker-based, oracle-driven attacks.  ...  Incorrect keys lead to setup and hold timing violations that SAT solvers cannot model by default.  ... 
arXiv:2005.10649v1 fatcat:s37zppylhfeqhftqotlft3a4iq

Advances in Logic Locking: Past, Present, and Prospects [article]

Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor
2022 IACR Cryptology ePrint Archive  
However, the security and strength of existing logic locking techniques have been constantly questioned by sophisticated logical and physical attacks that evolve in sophistication at the same rate as logic  ...  metrics to assess the efficacy, impact of locking in different levels of abstraction, threat model definition, resiliency against physical attacks, tampering, and the application of machine learning.  ...  point of view.  ... 
dblp:journals/iacr/KamaliAFT22 fatcat:qnskge42g5emrlasquo7yugdv4

An efficient finite-domain constraint solver for circuits

G. Parthasarathy, M. K. Iyer, K.-T. Cheng, L.-C. Wang
2004 Proceedings of the 41st annual conference on Design automation - DAC '04  
We describe how DPLL search is modified for search in combined integer and Boolean domains by using efficient finite-domain constraint propagation.  ...  This enables efficient combination of Boolean SAT and linear integer arithmetic solving techniques. We automatically use control and data-path abstraction in RTL descriptions.  ...  SAT based models of EDA problems are compact and can be adapted to various logic algebra [16] . A modern SAT solver can solve these problems efficiently.  ... 
doi:10.1145/996566.996628 dblp:conf/dac/ParthasarathyICW04 fatcat:ex2exwy4hbdrdovdxlu5kf5yom

Conflict Directed Lazy Decomposition [chapter]

Ignasi Abío, Peter J. Stuckey
2012 Lecture Notes in Computer Science  
In this paper we show how we can obtain the best of both worlds by lazily decomposing a complex constraint propagator using conflicts to direct it.  ...  Two competing approaches to handling complex constraints in satisfaction and optimization problems using SAT and LCG/SMT technology are: decompose the complex constraint into a set of clauses; or (theory  ...  NICTA is funded by the Australian Government as represented by the Department of Broadband, Communications and the Digital Economy and the Australian Research Council through the ICT Centre of Excellence  ... 
doi:10.1007/978-3-642-33558-7_8 fatcat:otqdiowp5bgy5bvu7k44bgu4ce

An Abstract Interpretation of DPLL(T) [chapter]

Martin Brain, Vijay D'Silva, Leopold Haller, Alberto Griggio, Daniel Kroening
2013 Lecture Notes in Computer Science  
This architecture enables modern solvers to combine the performance benefits of propositional satisfiability solvers and conjunctive theory solvers.  ...  Our characterisation allows a new understanding of dpll(t) as an instance of an abstract procedure to combine reasoning engines beyond propositional solvers and conjunctive theory solvers.  ...  Propositional models are enumerated on-the-fly by a sat solver rather than computed in a single step; the reduction to ⊥ is computed and checked by a theory solver.  ... 
doi:10.1007/978-3-642-35873-9_27 fatcat:hfixi2zy2bc27pvrc4srktbbmm

Fast, Flexible, and Minimal CTL Synthesis via SMT [chapter]

Tobias Klenze, Sam Bayless, Alan J. Hu
2016 Lecture Notes in Computer Science  
We show how to formulate CTL model checking in terms of "monotonic theories", enabling us to use the SAT Modulo Monotonic Theories (SMMT) [5] framework to build an efficient SAT-modulo-CTL solver.  ...  CTL synthesis [8] is a long-standing problem with applications to synthesising synchronization protocols and concurrent programs.  ...  This work was supported in part by a grant from the Natural Sciences and Engineering Research Council of Canada. We also thank Javier Esparza for his encouragement and helpful advice.  ... 
doi:10.1007/978-3-319-41528-4_8 fatcat:hqjdzwzaprgwtmoojkmbszhxqa

A Comprehensive Test Pattern Generation Approach Exploiting SAT Attack for Logic Locking [article]

Yadi Zhong, Ujjwal Guin
2022 arXiv   pre-print
In this paper, we propose a novel test pattern generation approach using the powerful SAT attack on logic locking. A stuck-at fault is modeled as a locked gate with a secret key.  ...  Our modeling of stuck-at faults preserves the property of fault activation and propagation. We show that the input pattern that determines the key is a test for the stuck-at fault.  ...  Any opinions, findings, conclusions, or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation.  ... 
arXiv:2204.11307v2 fatcat:7hbd5zcy2relnjvgmkkha5azym

Counterexample Guided Inductive Synthesis Modulo Theories [chapter]

Alessandro Abate, Cristina David, Pascal Kesseli, Daniel Kroening, Elizabeth Polgreen
2018 Lecture Notes in Computer Science  
We propose a new approach to program synthesis that combines the strengths of a counterexample-guided inductive synthesizer with those of a theory solver, exploring the solution space more efficiently  ...  Program synthesis is the mechanised construction of software.  ...  DPLL(T ) DPLL(T ) is an extension of the DPLL algorithm, used by most propositional SAT solvers, by a theory T . We give a brief overview of DPLL(T ) and compare DPLL(T ) with CEGIS(T ).  ... 
doi:10.1007/978-3-319-96145-3_15 fatcat:6poudpjlwzhcvnmegvreweav2i

Automatic Generation of Propagation Complete SAT Encodings [chapter]

Martin Brain, Liana Hadarean, Daniel Kroening, Ruben Martins
2015 Lecture Notes in Computer Science  
Almost all applications of SAT solvers generate Boolean formulae from higher level expression graphs by encoding the semantics of each operation or relation into propositional logic.  ...  This paper gives an abstract satisfaction based formalisation of one aspect of encoding quality, the propagation strength, and shows that propagation complete SAT encodings can be modelled by our formalism  ...  The views, opinions, and/or findings contained in this article are those of the authors and should not be interpreted as representing the official views or policies of the Department of Defense or the  ... 
doi:10.1007/978-3-662-49122-5_26 fatcat:tbehj2iedza23ed3kve47wwcom

Reconfigurable Hardware SAT Solvers: A Survey of Systems [chapter]

Iouliia Skliarova, António B. Ferrari
2003 Lecture Notes in Computer Science  
Such computational systems use high-capacity programmable logic devices and are based on processing units customized to the requirements of a particular application.  ...  The analysis and classification of existing systems has been performed according to such criteria as algorithmic issues, reconfiguration modes, the execution model, the programming model, logic capacity  ...  Fig. 4 . 4 The high-level view of the SAT solver proposed by Suyama et al.  ... 
doi:10.1007/978-3-540-45234-8_46 fatcat:jqgr35ub7vh2nh2pfena66ovoe

Improvements to combinational equivalence checking

Alan Mishchenko, Satrajit Chatterjee, Robert Brayton, Niklas Een
2006 Computer-Aided Design (ICCAD), IEEE International Conference on  
This paper improves on this method by (a) using more intelligent simulation, (b) using CNF-based SAT with circuit-based decision heuristics, and (c) interleaving SAT with low-effort logic synthesis.  ...  State-of-the-art methods use simulation and BDD/SAT sweeping on the input side (i.e. proving equivalence of some internal nodes in a topological order), interleaved with attempts to run SAT on the output  ...  Acknowledgement This research was supported in part by SRC contract 1361.001, NSF contract CCR-0312676, and by the California Micro program with our industrial sponsors, Altera, Intel, Magma, and Synplicity  ... 
doi:10.1145/1233501.1233679 dblp:conf/iccad/MishchenkoCBE06 fatcat:6y5cydbginfw5b7yepxoywobi4

Improvements to Combinational Equivalence Checking

Alan Mishchenko, Satrajit Chatterjee, Robert Brayton, Niklas Een
2006 Computer-Aided Design (ICCAD), IEEE International Conference on  
This paper improves on this method by (a) using more intelligent simulation, (b) using CNF-based SAT with circuit-based decision heuristics, and (c) interleaving SAT with low-effort logic synthesis.  ...  State-of-the-art methods use simulation and BDD/SAT sweeping on the input side (i.e. proving equivalence of some internal nodes in a topological order), interleaved with attempts to run SAT on the output  ...  Acknowledgement This research was supported in part by SRC contract 1361.001, NSF contract CCR-0312676, and by the California Micro program with our industrial sponsors, Altera, Intel, Magma, and Synplicity  ... 
doi:10.1109/iccad.2006.320087 fatcat:qf323sofv5cv7facaw2gvcl7vm

A SAT-Based Decision Procedure for Mixed Logical/Integer Linear Problems [chapter]

Hossein M. Sheini, Karem A. Sakallah
2005 Lecture Notes in Computer Science  
In our approach the linear constraints are viewed as special literals and replaced by binary "indicator" variables to generate a pure logical problem.  ...  The resulting problem is subsequently solved using a SAT search procedure which invokes the linear UTVPI solver to incrementally check the consistency of the UTVPI constraints whenever any of the indicator  ...  Acknowledgment This work was funded in part by the National Science Foundation (NSF) under ITR grant No. 0205288.  ... 
doi:10.1007/11493853_24 fatcat:vjutljnpvnaujap2epiotfcv2i

Reconfigurable hardware SAT solvers: a survey of systems

I. Skliarova, A. de Brito Ferrari
2004 IEEE transactions on computers  
Such computational systems use high-capacity programmable logic devices and are based on processing units customized to the requirements of a particular application.  ...  The analysis and classification of existing systems has been performed according to such criteria as algorithmic issues, reconfiguration modes, the execution model, the programming model, logic capacity  ...  This work was supported by the Portuguese Foundation of Science and Technology under grants No. FCT-PRAXIS XXI/BD/ 21353/99 and No. POSI/43140/CHS/2001.  ... 
doi:10.1109/tc.2004.102 fatcat:msmjq2ryo5dfdmuada42vha53a

SAT-Based Verification Methods and Applications in Hardware Verification [chapter]

Aarti Gupta, Malay K. Ganai, Chao Wang
2006 Lecture Notes in Computer Science  
Verification methods based on Boolean Satisfiability (SAT) have emerged as a promising alternative to BDD-based symbolic model checking methods.  ...  We also describe practical experiences with these methods implemented in our verification platform called VeriSol (formerly DiVer), which has been used successfully in industry practice.  ...  Different variants of temporal logics have become popular, such as Linear Temporal Logic (LTL) and Computation Tree Logic (CTL), depending on whether a linear or a branching view of time is considered,  ... 
doi:10.1007/11757283_5 fatcat:5kb2pmlvjvat5ljeei2fflzufa
« Previous Showing results 1 — 15 out of 942 results