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Challenges of Return-Oriented-Programming on the Xtensa Hardware Architecture

Kai Lehniger, Marcin J. Aftowicz, Peter Langendorfer, Zoya Dyka
2020 2020 23rd Euromicro Conference on Digital System Design (DSD)  
This paper shows how the Xtensa architecture can be attacked with Return-Oriented-Programming (ROP).  ...  This paper purely focuses on how the properties of the architecture itself can be exploited to chain gadgets and not on specific attacks or a gadget catalog.  ...  ACKNOWLEDGMENT This work was supported by the Federal Ministry of Education and Research (BMBF) under research grant number 01IS18065E.  ... 
doi:10.1109/dsd51259.2020.00034 dblp:conf/dsd/LehnigerALD20 fatcat:guqot3ehwjfihaf4zf55hxwsvq

Verification of configurable processor cores

Marinés Puig-Medina, Gülbin Ezer, Pavlos Konas
2000 Proceedings of the 37th conference on Design automation - DAC '00  
The simulation-based approach uses directed diagnostics and pseudo-random program generators both of which are tailored to specific processor instances.  ...  The results of the analysis show that our methodology achieves good verification coverage of the processor implementation.  ...  The authors are especially grateful to the entire hardware team for building this verification methodology and for their insightful comments on drafts of the paper.  ... 
doi:10.1145/337292.337527 dblp:conf/dac/Puig-MedinaEK00 fatcat:kpkv4qfykvcg7ncpi3upk6el6m

Processor Modeling and Design Tools [chapter]

Prabhat Mishra, Nikil Dutt
2006 Industrial Information Technology  
The goal is to find the best possible processor architecture for the given set of application programs under various design constraints such as cost, area, power and performance.  ...  The ADL specification is also used to perform various design automation tasks including hardware generation and functional verification of the processor.  ...  The content-oriented classification is based on the nature of the information an ADL can capture, whereas the objective-oriented classification is based on the purpose of an ADL.  ... 
doi:10.1201/9781420007947.ch8 fatcat:azirpu6yajf2dkvpiiqhecdise

Architecture description languages for programmable embedded systems

P. Mishra, N. Dutt
2005 IEE Proceedings - Computers and digital Techniques  
Architecture description languages (ADL) enable exploration of programmable architectures for a given set of application programs under various design constraints such as area, power and performance.  ...  The ADL specification is used to generate a variety of software tools and models facilitating exploration and validation of candidate architectures.  ...  The content-oriented classification is based on the nature of the information an ADL can capture, whereas the objective-oriented classification is based on the purpose of an ADL.  ... 
doi:10.1049/ip-cdt:20045071 fatcat:sznyga75n5hk3pongpmyrmffgq

Application-specific Processor Architecture: Then and Now

Peter Cappello
2007 Journal of Signal Processing Systems  
We first relate the architecture of systolic arrays to the technological and economic design forces acting on architects of special-purpose systems some 20 years ago.  ...  At base, they are the increasing complexity of technology and applications, the fragmenting of the general-purpose processor market, and the judicious use hardware configurability.  ...  Programming language One reason that GPP multicore architectures did not emerge sooner is because the Bproblem^of parallel programming had not been Bsolved.  ... 
doi:10.1007/s11265-007-0127-9 fatcat:dmcbpubj2rdajplt2j6sqcjmxu

Architectures of flexible symmetric key crypto engines—a survey

Lilian Bossuet, Michael Grand, Lubos Gaspar, Viktor Fischer, Guy Gogniat
2013 ACM Computing Surveys  
The flexibility of reconfigurable crypto processors and crypto coprocessors has reached new levels with the emergence of dynamically reconfigurable hardware architectures and tools.  ...  of the information to be protected and on the cost of protection.  ...  MAIN CRYPTO ENGINE DESIGN CHALLENGES Crypto engine design faces a number of challenges that have led to the emergence of new trends.  ... 
doi:10.1145/2501654.2501655 fatcat:h5pccigb35hfvinkrpn7s75gl4

Hardware/software co-design for energy-efficient seismic modeling

Jens Krueger, David Donofrio, John Shalf, Marghoob Mohiyuddin, Samuel Williams, Leonid Oliker, Franz-Josef Pfreund
2011 Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis on - SC '11  
These results point to the enormous potential energy advantages of our hardware/software co-design methodology.  ...  We have developed an FPGA-accelerated architectural simulation platform to accurately model the power and performance of the Green Wave design.  ...  We also thank Marty Deneroff who has provided a lot of advice and expertise on system design trade-offs and cost models for practical implementation.  ... 
doi:10.1145/2063384.2063482 dblp:conf/sc/KruegerDSMWOP11 fatcat:o2e6edp2ybcaxb6z3bs5wrovji

FPGA Prototyping and Design Evaluation of a NoC-Based MPSoC

Ridha SALEM, Yahia SALAH, Imed BENNOUR, Mohamed ATRI
2017 International Journal of Advanced Computer Science and Applications  
This led to the emergence of new interconnection architectures, like Network-on-Chip (NoC). NoCs have been proven to be a promising solution to the concerns of MPSoCs in terms of data parallelism.  ...  In this paper, we present an FPGA based on rapid prototyping in hardware/software co-design and design evaluation of a mixed HW/SW MPSoC using a NoC.  ...  Unlike conventional hardware prototyping approaches, FPGA-based prototyping of mixed hardware/software MPSoC architecture became an extremely challenging task.  ... 
doi:10.14569/ijacsa.2017.081139 fatcat:rzmmhjfpdjdm7jsfrt2u7q3swy

FPGA-accelerator system for computing biologically inspired feature extraction models

Michael DeBole, Yang Xiao, Chi-Li Yu, Ahmed Al Maashri, Matthew Cotter, Chaitali Chakrabarti, Vijaykrishnan Narayanan
2011 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR)  
The final system is shown to operate within a power budget of 3W while achieving up to 16.5X speedup over a pure embedded processor implementation.  ...  In this paper, we present an embedded implementation of a ventral visual pathway model, HMAX.  ...  This work is funded in part by The DARPA NeoVision 2 program. Ahmed Al Maashri is sponsored by a scholarship from the Government of Oman.  ... 
doi:10.1109/acssc.2011.6190106 dblp:conf/acssc/DeBoleXYACCN11 fatcat:gr2nko3ckbfrhezg4rhhzzedha

SoK: Enabling Security Analyses of Embedded Systems via Rehosting

Andrew Fasano, Tiemoko Ballo, Marius Muench, Tim Leek, Alexander Bulekov, Brendan Dolan-Gavitt, Manuel Egele, Aurélien Francillon, Long Lu, Nick Gregory, Davide Balzarotti, William Robertson
2021 Proceedings of the 2021 ACM Asia Conference on Computer and Communications Security  
One approach to enable dynamic analyses of embedded systems is to move software stacks from physical systems into virtual environments that sufficiently model hardware behavior.  ...  ., x86 desktop PCs), they can rarely be applied in the heterogeneous world of embedded systems.  ...  ACKNOWLEDGMENTS The authors wish to thank the following individuals for their contributions and support: Lindsey  ... 
doi:10.1145/3433210.3453093 fatcat:6n2oqca4abgjfeubk4d4ccostm

Application Specific Processors for Multimedia Applications

Muhammad Rashid, Ludovic Apvrille, Renaud Pacalet
2008 2008 11th IEEE International Conference on Computational Science and Engineering  
This paper evaluates an ASIP design methodology based on the extension of an existing instruction set and architecture described with LISA 2.0 language.  ...  A case study demonstrates the methodological approach for the JPEG algorithm and motion estimation encoding algorithm of H.264 encoding standard.  ...  The LISATek evaluation of the motion estimation subalgorithm was performed by Stephane Paris during his internship at LabSoc.  ... 
doi:10.1109/cse.2008.26 dblp:conf/cse/RashidAP08 fatcat:dvth5hprljccdg4exbzmabndky

Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform

Antonino Tumeo, Marco Branca, Lorenzo Camerini, Marco Ceriani, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
2009 2009 Asia and South Pacific Design Automation Conference  
Our framework eases the development cycle and enables the developers to focus directly on the problems posed by the programming model in the direction of the implementation of a production system.  ...  Multiprocessors on a chip are the reality of these days.  ...  ACKNOWLEDGMENTS Research partially funded by the European Community's Sixth Framework Programme, hArtes Project.  ... 
doi:10.1109/aspdac.2009.4796500 dblp:conf/aspdac/TumeoBCCMPFS09 fatcat:5sth3x5itfacti7zpnj3qhup3y

Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs

Süleyman Savas, Zain Ul-Abdin, Tomas Nordström
2018 Computers  
However, designing heterogeneous architectures is a challenging task due to the complexity of these architectures.  ...  As a result, exploring the design space of heterogeneous manycore architectures through simulations becomes increasingly challenging. Further discussion on manycore simulation can be found in [13] .  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/computers7020027 fatcat:qktz2c36bbcxnj4bdrihwt35vq

HASHI: An Application Specific Instruction Set Extension for Hashing

Oliver Arnold, Sebastian Haas, Gerhard P. Fettweis, Benjamin Schlegel, Thomas Kissinger, Tomas Karnagel, Wolfgang Lehner
2014 Very Large Data Bases Conference  
Hashing is one of the most relevant operations within query processing.  ...  In this paper, we present a way to significantly improve performance and energy e ciency of hash operations using specialized instruction set extensions for the Tensilica Xtensa LX5 core.  ...  ACKNOWLEDGEMENTS This work has been supported by the state of Saxony under grant of ESF 100098198 (IMData) and 100111037 (SREX) and the German Research Foundation (DFG) within the Cluster of Excellence  ... 
dblp:conf/vldb/ArnoldHFSKKL14 fatcat:z7w5m24s2ff5vbxpt5g5mxgrxi

SMASHUP: a toolchain for unified verification of hardware/software co-designs

Florian Lugou, Ludovic Apvrille, Aurélien Francillon
2016 Journal of Cryptographic Engineering  
Formally and consistently proving the efficiency of these solutions raises challenges since software and hardware verifications approaches generally rely on different representations.  ...  Next, it proposes an evaluation of formal verification methods that have already been proposed for mixed hardware/software systems, with regards to the ideal method.  ...  While having an instruction-accurate model is a first step, we are still not working on a low enough level to model attacks such as Return Oriented Programming, which would require a representation that  ... 
doi:10.1007/s13389-016-0145-2 fatcat:3frsj6yb2batxmrlhquazcrmcu
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