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Design of a bus-based shared-memory multiprocessor DICE

Gyungho Lee, Bland W Quattlebaum, Sangyeun Cho, Larry L Kinney
1999 Microprocessors and microsystems  
DICE is a shared-bus multiprocessor based on a distributed shared-memory architecture, known as cache-only memory architecture (COMA).  ...  for future shared-bus multiprocessor designs  ...  for the future shared-bus multiprocessor architecture.  ... 
doi:10.1016/s0141-9331(98)00097-0 fatcat:gmluftwjg5g3ximidir4rq3b7y

Coherence and Replacement Protocol of DICE—A Bus-Based COMA Multiprocessor

Sangyeun Cho, Jinseok Kong, Gyungho Lee
1999 Journal of Parallel and Distributed Computing  
DICE, a shared-bus multiprocessor, utilizes cache only memory architecture (COMA) to effectively decrease the speed gap between modern high-performance microprocessors and the bus.  ...  We present performance results that show a drastic reduction in global bus traffic compared to a traditional shared-bus multiprocessor architecture. 1999 Academic Press, Inc.  ...  Sangyeun Cho was supported in part by a fellowship from the Korea Foundation for Advanced Studies.  ... 
doi:10.1006/jpdc.1998.1524 fatcat:fdu7qc55k5f2jazhvs5sbazdwi

Moving paragon™ operating system to a new hardware platform

A.K. Pfiffer
1998 Computers and Mathematics with Applications  
The new hardware platform differs from the Paragon System in several areas, including processor architecture, multiprocessor capabilities, I/O support, and interconnect technology.  ...  Performance metrics for critical-path message-passing software and other OS microfunctions are compared to the existing Paragon platform.  ...  ASMP and APIC Paragon OS for the Intel Architecture now supports multiprocessor systems that are compliant with the Intel Multiprocessor Spec.  ... 
doi:10.1016/s0898-1221(98)00030-3 fatcat:xzgl6ntv7zclne3pk726zd2ea4

The MIT Alewife Machine: A Large-Scale Distributed-Memory Multiprocessor [chapter]

Anant Agarwal, David Chaiken, Kirk Johnson, David Kranz, John Kubiatowicz, Kiyoshi Kurihara, Beng-Hong Lim, Gino Maa, Dan Nussbaum
1992 Scalable Shared Memory Multiprocessors  
The goal of the Alewife project is to discover and to evaluate techniques for automatic locality management in scalable multiprocessors.  ...  The prototype Alewife system will attach to a host SUN backplane by interfacing a network switch to the VME bus.  ... 
doi:10.1007/978-1-4615-3604-8_13 fatcat:7js5232i3naevnf45t4qmrxtb4

Scalable, parallel computers: Alternatives, issues, and challenges

Gordon Bell
1994 International journal of parallel programming  
This amounts to a factor of 17% and 36% per year performance increase for processor and system (including multiprocessor), respectively.  ...  KEY WORDS: Scalable multiprocessors and multicomputers; massive parallelism; distributed or shared virtual memory; high performance computers; computer architecture.  ...  Multiprocessors (Fig. l a ) communicate by accessing a single, shared common memory.  ... 
doi:10.1007/bf02577791 fatcat:jnvgpsftabcnnabkmpcm5kifqq

Performance evaluation of a java chip-multiprocessor

Christof Pitter, Martin Schoeberl
2008 2008 International Symposium on Industrial Embedded Systems  
Chip multiprocessing design is an emerging trend for embedded systems. In this paper, we introduce a Java multiprocessor system-on-chip called JopCMP.  ...  Our results illustrate the promises and limits of the proposed multiprocessor architecture concerning synchronization, memory bandwidth and caching.  ...  ACKNOWLEDGEMENT We thank Wolfgang Puffitsch for executing the benchmarks on the picoJava processor and providing the result for our  ... 
doi:10.1109/sies.2008.4577678 dblp:conf/sies/PitterS08 fatcat:exlwkqcnw5gutmjk36eqe54kny

An Implementation of real-time phased array radar fundamental functions on DSP-focused, high performance embedded computing platform

Xining Yu, Yan Zhang, Ankit Patel, Allen Zahrai, Mark Weber, Kenneth I. Ranney, Armin Doerry
2016 Radar Sensor Technology XX  
communication.  ...  This paper investigates the feasibility of a backend design for real-time, multiple-channel processing digital phased array system, particularly for high-performance embedded computing platforms constructed  ...  Scalable backend System Architecture As mentioned earlier, the features of a basic radar processing chain allow for independent and parallel processing task divisions.  ... 
doi:10.1117/12.2224058 fatcat:xq7ov26uq5dnxlusywj7qbuegi

An Implementation of Real-Time Phased Array Radar Fundamental Functions on a DSP-Focused, High-Performance, Embedded Computing Platform

Xining Yu, Yan Zhang, Ankit Patel, Allen Zahrai, Mark Weber
2016 Aerospace (Basel)  
the Serial RapidIO protocol in backplane communication.  ...  An MTCA system contains one or more chassis into which multiple AMCs can be inserted. Each AMC communicates with others via the backplane of a chassis.  ...  Scalable Backend System Architecture As mentioned earlier, the features of a basic radar processing chain allow for independent and parallel processing task divisions.  ... 
doi:10.3390/aerospace3030028 fatcat:3ro5kpqbavew3cqjp2cdjt3koe

A Cache coherence protocol for MIN-based multiprocessors

Mazin S. Yousif, Chita R. Das, Matthew J. Thazhuthaveetil
1994 Journal of Supercomputing  
This model is solved for processor and coherence bus utilizations using the mean value analysis (MVA) technique with shared-blocks steady state probabilities (phase 1) and communication delays (phase 2  ...  The performance of our system is compared to that of a system with an equivalent-sized unified cache and with a multiprocessor implementing a directory-based coherence protocol.  ...  Scalability is a key concern in multiprocessor design.  ... 
doi:10.1007/bf01204660 fatcat:ari6h2fbhrcoriz6znxzlsjv2a

On-chip interconnect schemes for reconfigurable system-on-chip

Andy S. Lee, Neil W. Bergmann, Derek Abbott, Kamran Eshraghian, Charles A. Musca, Dimitris Pavlidis, Neil Weste
2004 Microelectronics: Design, Technology, and Packaging  
On-chip communication architectures can have a great influence on the speed and area of System-on-Chip designs, and this influence is expected to be even more pronounced on reconfigurable System-on-Chip  ...  To date, little research has been conducted on the performance implications of different on-chip communication architectures for rSoC designs.  ...  This is easy to achieve for systems where multiprocessor or duplicated computational units are used, but inefficient for general systems.  ... 
doi:10.1117/12.523334 fatcat:ywworo2ipvfgbggssxuedgj33q

Distributed shared memory: concepts and systems

J. Protic, M. Tomasevic, V. Milutinovic
1996 IEEE Parallel & Distributed Technology Systems & Applications  
His research interests are computer architectures, multiprocessor systems, and distributed shared-memory systems. He can be reached a t etomasev@ubbg.etf.bg.ac.yu.  ...  Her research interests are in computer architecture, distributed systems, and performance analysis. She can be reached at jeca@ubbg.etf.bg.ac.yu.  ...  We also want to thank Vojislav Protiit for his help in providing up-to-date literature, and Liviu Iftode, who kindly provided some of his most recent papers.  ... 
doi:10.1109/88.494605 fatcat:56jusk7vobepvhcvroadujiiae

Structured interconnect architecture

Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh
2004 Proceedins of the 14th ACM Great Lakes symposium on VLSI - GLSVLSI '04  
for SoC interconnect that does not suffer from the non-scalability aspect of the buses in regards to the clock cycle.  ...  Systems having multiple smaller buses, integrated through repeaters or bridges, are possible alternatives. But these kinds of solutions are ad-hoc in nature.  ...  ACKNOWLEDGMENTS The authors wish to thank Micronet, PMC-Sierra, Gennum, and NSERC for their financial support and the CMC for providing access to CAD tools.  ... 
doi:10.1145/988952.988999 dblp:conf/glvlsi/GrecuPIS04 fatcat:tvfcgh4ryrefjnteouz6ihdypy

A Scalable Server Architecture for Next-Generation Heterogeneous Compute Clusters

Rene Griessl, Meysam Peykanu, Jens Hagemeyer, Mario Porrmann, Stefan Krupop, Micha vor dem Berge, Thomas Kiesel, Wolfgang Christmann
2014 2014 12th IEEE International Conference on Embedded and Ubiquitous Computing  
Additionally, serial high-speed links between the FPGA-based microservers are used as communication accelerators for highbandwidth, low-latency data transmission.  ...  In this paper, we present a novel highly-scalable, heterogeneous server architecture that seamlessly integrates arbitrary combinations of microservers based on general purpose CPUs, low power mobile CPUs  ...  RECS SYSTEM ARCHITECTURE The RECS ® |Box system architecture is designed using a modular approach, resulting in a highly scalable system.  ... 
doi:10.1109/euc.2014.29 dblp:conf/euc/GriesslPHPKBKC14 fatcat:eys22dtzxbarll5mxemmtmqvbu

Logic emulation with virtual wires

J. Babb, R. Tessier, M. Dahl, S.Z. Hanono, D.M. Hoki, A. Agarwal
1997 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
He led the Alewife multiprocessor and the Virtual Wires projects at MIT.  ...  ., which was aimed at productizing the VirtualWires technology for logic emulation.  ...  System size is scaled by attaching additional boards on any of the four sides of the current system boards, without the need for crossbars or esoteric backplane technology.  ... 
doi:10.1109/43.640619 fatcat:xslresgiivbi7pjbujhtecivii

Logic Emulation with Virtual Wires Manuscript received March 20, 1995; revised April 26, 1996 and June 17, 1997. This work was supported by ARPA Contract N00014-91-J-1698 and NSF Grant MIP-9012773. This paper was recommended by Associate Editor C.-K. Cheng. Publisher Item Identifier S 0278-0070(97)07006-1 [chapter]

Jonathan Babb, Russell Tessier, Matthew Dahl, Silvina Zimi Hanono, David M. Hoki, Anant Agarwal
2002 Readings in Hardware/Software Co-Design  
He led the Alewife multiprocessor and the Virtual Wires projects at MIT.  ...  ., which was aimed at productizing the VirtualWires technology for logic emulation.  ...  System size is scaled by attaching additional boards on any of the four sides of the current system boards, without the need for crossbars or esoteric backplane technology.  ... 
doi:10.1016/b978-155860702-6/50058-2 fatcat:z7simtmezreitcvsypfzt2yf6e
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