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Centip3De: A 64-Core, 3D Stacked Near-Threshold System

Ronald G. Dreslinski, David Fick, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory Chen (+3 others)
<span title="">2013</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/gvjkwgwwvnakpbfssxpqjozbqm" style="color: black;">IEEE Micro</a> </i> &nbsp;
128-core system Bus System University of Michigan Centip3De System Overview  3D-Stacked DRAM  Tezzaron Octopus  1 control layer  130nm CMOS  1 Gb bitcell layers  Up to two layers  ...  1 Core Mode 1 Core Boosted 3 Cores Gated University of Michigan [1] http://arm.com/products/processors/cortex-a/cortex-a9.php, ARM Ltd, 2011.Conclusion  Near threshold computing (NTC) Need  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/mm.2013.4">doi:10.1109/mm.2013.4</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/3pfdq3kczreq5cjkmdyprfwc6y">fatcat:3pfdq3kczreq5cjkmdyprfwc6y</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170830072626/http://web.eecs.umich.edu/~tnm/trev_test/papersPDF/2012.8.centip3deHotChips2012.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/a5/a2/a5a2cbc0a46f8dc7b850b0930b37c917a629a573.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/mm.2013.4"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Centip3De: A 64-core, 3D stacked, near-threshold system

Ronald G. Dreslinski, David Fick, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory Chen (+3 others)
<span title="">2012</span> <i title="IEEE"> 2012 IEEE Hot Chips 24 Symposium (HCS) </i> &nbsp;
128-core system Bus System University of Michigan Centip3De System Overview  3D-Stacked DRAM  Tezzaron Octopus  1 control layer  130nm CMOS  1 Gb bitcell layers  Up to two layers  ...  1 Core Mode 1 Core Boosted 3 Cores Gated University of Michigan [1] http://arm.com/products/processors/cortex-a/cortex-a9.php, ARM Ltd, 2011.Conclusion  Near threshold computing (NTC) Need  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/hotchips.2012.7476490">doi:10.1109/hotchips.2012.7476490</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/hirj2n2m5na3hh673kyg362ueu">fatcat:hirj2n2m5na3hh673kyg362ueu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170830072626/http://web.eecs.umich.edu/~tnm/trev_test/papersPDF/2012.8.centip3deHotChips2012.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/a5/a2/a5a2cbc0a46f8dc7b850b0930b37c917a629a573.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/hotchips.2012.7476490"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores

David Fick, Ronald G. Dreslinski, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory Chen (+3 others)
<span title="">2012</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/y4cu6znedbgxbdecknzpgfmoli" style="color: black;">2012 IEEE International Solid-State Circuits Conference</a> </i> &nbsp;
This paper proposes the use of near-threshold computing (NTC) to address this issue in a stacked 3D system.  ...  In NTC, cores are operated near the threshold voltage (~200mV above Vth) to optimally balance power and performance [1].  ...  The fabricated Centip3De system consists of two stacked dies with 64 ARM M3 near-threshold cores that make up 16 four-core clusters, each connected to a 4way 1kB instruction cache and a 4-way 8kB data  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/isscc.2012.6176970">doi:10.1109/isscc.2012.6176970</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/isscc/FickDGKSFSLKLWCMSB12.html">dblp:conf/isscc/FickDGKSFSLKLWCMSB12</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/amqsy5ivrfepfmess5glfxpivq">fatcat:amqsy5ivrfepfmess5glfxpivq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170923002634/http://web.eecs.umich.edu/~tnm/trev_test/papersPDF/2012.02.centip3de_ISSCC.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/62/47/6247ba48c3227c284c87a1fb2e89a9f445148067.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/isscc.2012.6176970"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Centip3De

Ronald G. Dreslinski, Nurrachman Liu, Michael Wieckowski, Gregory Chen, Dennis Sylvester, David Blaauw, Trevor Mudge, David Fick, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik (+3 others)
<span title="2013-11-01">2013</span> <i title="Association for Computing Machinery (ACM)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/i6iajiiyxvgz3ob6jwcn2pufni" style="color: black;">Communications of the ACM</a> </i> &nbsp;
Specifically, we will discuss the design and test of Centip3De, a large-scale 3D-stacked near-threshold chip multiprocessor.  ...  To address the thermal issues that arise with 3D integration, this paper also evaluates the use of near-threshold computing-operating the system at a supply voltage just above the threshold voltage of  ...  /throughput/singlethread performance space. overall, Centip3De achieves a best energy efficiency of 3930 DmiPs/ 3930 DMIPS/W Configurable Near-Threshold 3D Stacked System With 64 ARM Cortex-M3 Cores"  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/2524713.2524725">doi:10.1145/2524713.2524725</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/74pzpfaqgbftffd7iw36ma6xaa">fatcat:74pzpfaqgbftffd7iw36ma6xaa</a> </span>
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Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS

David Fick, Ronald G. Dreslinski, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory Chen (+3 others)
<span title="">2013</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/cz5rf4o3ezafnl4kjpq643g32e" style="color: black;">IEEE Journal of Solid-State Circuits</a> </i> &nbsp;
We present Centip3De, a large-scale 3D CMP with a cluster-based near-threshold computing (NTC) architecture. Centip3De uses a 3D stacking technology in conjunction with 130 nm CMOS.  ...  Measured results for a two-layer, 64-core system are discussed, with the system achieving 3930 DMIPS/W energy efficiency, which is > 3x improvement over traditional operation at full supply voltage.  ...  In this work, we propose using near-threshold computing (NTC) in 3D design to address these issues [14] , [15] .  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/jssc.2012.2222814">doi:10.1109/jssc.2012.2222814</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/3wc3rliiajddnmk432u5223ldm">fatcat:3wc3rliiajddnmk432u5223ldm</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170706094935/http://web.eecs.umich.edu/~tnm/trev_test/papersPDF/2013.01.Centip3DE.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/54/dd/54dde21f1a6dc23d33536816b952e92ed322549a.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/jssc.2012.2222814"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips

Yuang Zhang, Li Li, Zhonghai Lu, Axel Jantsch, Yuxiang Fu, Minglun Gao
<span title="">2014</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/kucxvipvevedfgtsl3pnvxorse" style="color: black;">2014 IEEE International Symposium on Circuits and Systems (ISCAS)</a> </i> &nbsp;
Experiment results on 16-core 3D NoC systems show that the tightly mixed NUCA could provide up to 31.71% and on average 5.95% performance improvement compared to a base 3D NUCA scheme.  ...  Our analysis and experimental results provide a guideline to design efficient 3D NoCs with stacking NUCA.  ...  [3] [4] propose a low power 64-core system that is called Centip3De. Centip3De has two stacked dies with a layer of 64 ARM M3 near-threshold cores and a cache layer.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/iscas.2014.6865546">doi:10.1109/iscas.2014.6865546</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/iscas/ZhangLLJFG14.html">dblp:conf/iscas/ZhangLLJFG14</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/plwrbmctsvh2nlhzedoezisrmq">fatcat:plwrbmctsvh2nlhzedoezisrmq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170808121942/http://jantsch.se/AxelJantsch/papers/2014/YuangZhang-ISCAS.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/b1/ba/b1ba2350900d3e800c09de5dc1430513c81bf3d6.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/iscas.2014.6865546"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Selected Research from Hot Chips 24

Christos Kozyrakis, Rumi Zahir
<span title="">2013</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/gvjkwgwwvnakpbfssxpqjozbqm" style="color: black;">IEEE Micro</a> </i> &nbsp;
Power-efficient multicore chip In ''Centip3De: A 64-Core, 3D Stacked Near-Threshold System,'' Ronald G.  ...  Centip3De uses throughsilicon vias for 3D integration of 128 cores with 256 Mbytes of DRAM memory.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/mm.2013.44">doi:10.1109/mm.2013.44</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/xbpxyxfbzbbldkvk45rrghufxa">fatcat:xbpxyxfbzbbldkvk45rrghufxa</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20140318032341/http://www.computer.org/csdl/mags/mi/2013/02/mmi2013020006.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/6f/93/6f936d28f2af093404dc98cfe61c6827a83dfe7f.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/mm.2013.44"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

3D-MMC: A Modular 3D Multi-Core Architecture with Efficient Resource Pooling

Tiansheng Zhang, Alessandro Cevrero, Giulia Beanato, Panagiotis Athanasopoulos, Ayse K. Coskun, Yusuf Leblebici
<span title="">2013</span> <i title="IEEE Conference Publications"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/qjrrvry5ubgdlarkymvlxuip6m" style="color: black;">Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE), 2013</a> </i> &nbsp;
Our 3D system is a low-power 3D Modular Multi-Core (3D-MMC) architecture built by vertically stacking identical layers.  ...  This paper demonstrates a fully functional hardware and software design for a 3D stacked multi-core system for the first time.  ...  and the stacked memory die contains 256KB SRAM, and Centip3De [9] , a configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.7873/date.2013.257">doi:10.7873/date.2013.257</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/date/ZhangCBACL13.html">dblp:conf/date/ZhangCBACL13</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/mwce32wwmfdjbinwn3bh5qnlnm">fatcat:mwce32wwmfdjbinwn3bh5qnlnm</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170812061448/http://www.bu.edu/peaclab/files/2014/03/zhang_DATE13.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/7f/26/7f265b7fbc7660b71140d09ac11a78bdd4fca953.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.7873/date.2013.257"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Thoughts on Winning the 2014 Eckert-Mauchly Award

Trevor Mudge
<span title="">2015</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/gvjkwgwwvnakpbfssxpqjozbqm" style="color: black;">IEEE Micro</a> </i> &nbsp;
To test the idea, a group of us, led by Ron Dreslinski and Dave Fick, designed and fabricated a 128-core NTC multiprocessor, Centip3De, that stacked processors, caches, and DRAMs. 10 It was a large undertaking  ...  More recently, we started to look at operating logic at much lower voltage levels-a regime we called near threshold computing (NTC).  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/mm.2015.68">doi:10.1109/mm.2015.68</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/j7jjd2sgf5adhj3flqnuutmrbi">fatcat:j7jjd2sgf5adhj3flqnuutmrbi</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180725084058/https://ieeexplore.ieee.org/ielx7/40/7129787/07130458.pdf?tp=&amp;arnumber=7130458&amp;isnumber=7129787" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/ac/b2/acb2076bd1fa0ef36dc449cdc2bf1b3df4ce7c8d.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/mm.2015.68"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Overview of Swallow --- A Scalable 480-core System for Investigating the Performance and Energy Efficiency of Many-core Applications and Operating Systems [article]

Simon J. Hollis, Steve Kerrison
<span title="2015-04-23">2015</span> <i > arXiv </i> &nbsp; <span class="release-stage" >pre-print</span>
We present Swallow, a scalable many-core architecture, with a current configuration of 480 x 32-bit processors.  ...  The system provides 240GIPS with each core consuming 71--193mW, dependent on workload. Power consumption per instruction is lower than almost all systems of comparable scale.  ...  The Centip3De system [12] aims to use 3-D stacked dies to implement a 64-core system based on the ARM Cortex-M3 processor.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/1504.06357v1">arXiv:1504.06357v1</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/kggrakzltrchzc5xhx3r33yngm">fatcat:kggrakzltrchzc5xhx3r33yngm</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20191022043934/https://arxiv.org/pdf/1504.06357v1.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/f0/bf/f0bf6529eb6c52aa67b400445001a77972a13461.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/1504.06357v1" title="arxiv.org access"> <button class="ui compact blue labeled icon button serp-button"> <i class="file alternate outline icon"></i> arxiv.org </button> </a>

Eurolab-4-HPC Long-Term Vision on High-Performance Computing [article]

Theo Ungerer, Paul Carpenter
<span title="2018-07-11">2018</span> <i > arXiv </i> &nbsp; <span class="release-stage" >pre-print</span>
The objective of the Eurolab-4-HPC vision is to provide a long-term roadmap from 2023 to 2030 for High-Performance Computing (HPC).  ...  This document presents the "EuroLab-4-HPC Long-Term Vision on High-Performance Computing" of August 2017, a road mapping effort within the EC CSA1 Eurolab-4-HPC that targets potential changes in hardware  ...  "Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores". In: 2012 IEEE International Solid-State Circuits Confer- ence. Feb. 2012, pp. 190-192.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/1807.04521v1">arXiv:1807.04521v1</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/5neetrgubjhnvcajcktpkohrzq">fatcat:5neetrgubjhnvcajcktpkohrzq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20191020044256/https://arxiv.org/pdf/1807.04521v1.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/e0/5a/e05a9ff1651552952917e66a3de7b695ee036fd2.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/1807.04521v1" title="arxiv.org access"> <button class="ui compact blue labeled icon button serp-button"> <i class="file alternate outline icon"></i> arxiv.org </button> </a>

SpiNNaker - programming model

<span title="">2014</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/5jlmyrayyrdazh5awdlsoec77q" style="color: black;">IEEE transactions on computers</a> </i> &nbsp;
Even with isolated printed circuit boards of 864 cores, interesting capabilities are emerging. This paper is the third of a series charting the development trajectory of the system.  ...  SpiNNaker is a multi-core computing engine, with a bespoke and specialised communication infrastructure that supports almost perfect scalability up to a hard limit of 2 16 Â 18 ¼ 1;179;648 cores.  ...  Centip3De is a 130 nm stacked 3D near-threshold computing (NTC) chip design that distributes 64 ARM Cortex-M3 processors over four cache/core layers connected by face-to-face interface ports [7] .  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tc.2014.2329686">doi:10.1109/tc.2014.2329686</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/gas4bqmryzblnjymj3dubab7hy">fatcat:gas4bqmryzblnjymj3dubab7hy</a> </span>
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HETEROGENEOUS ARCHITECTURES FOR PARALLEL ACCELERATION Heterogeneous Architectures for Parallel Acceleration

Presentata, Dott Conti, Coordinatore Dottorato, Relatore Prof, Vanelli Alessandro, Coralli, Luca Benini, Francesco Conti, W Shakespeare, Hamlet
<span class="release-stage">unpublished</span>
To enable a new generation of digital computing applications, the greatest challenge is to provide a better level of energy efficiency (intended as the performance that a system can provide within a certain  ...  This constraint applies to digital system across all scales, starting from ultra-low power implanted devices up to datacenters for high-performance computing and for the "cloud".  ...  The same approach is followed by Centip3de [3] . Centip3de consists of a large scale 3D-integrated fabric of clusters of Cortex M3 cores.  ... 
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OPTIMIZATION TECHNIQUES FOR PARALLEL PROGRAMMING OF EMBEDDED MANY-CORE COMPUTING PLATFORMS OPTIMIZATION TECHNIQUES FOR PARALLEL PROGRAMMING OF EMBEDDED MANY-CORE COMPUTING PLATFORMS

Presentata, Dott Giuseppe, Tagliavini Coordinatore, Dottorato Relatore, Vanelli Alessandro, Coralli, Benini Luca, Dott Correlatori, Marongiu, Relatore Candidato, Chiar Mo, Benini Luca (+4 others)
<span title="">2017</span> <span class="release-stage">unpublished</span>
Infine il ringraziamento più importante va a Francesca, la mia compagna e l'amore della mia vita. Senza il suo supporto e la sua fiducia nelle mie capacità non avrei mai intrapreso questo percorso.  ...  To match conflicting requirements for energy consumption and performance, near-threshold multi-core systems have been recently pro- posed [127] [95] featuring 8 PEs and a TCDM composed by 16 6T-SRAM  ...  Centip3de is a clustered-based fabric of Cortex M3 cores, while PULP presents a similar design based on OpenRISC cores.  ... 
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