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Properties of BaBi2Ta2O9 thin films prepared by chemical solution deposition technique for dynamic random-access memory applications
1999
Journal of Materials Research
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The high dielectric constant, low dielectric loss and low leakage current density suggest the suitability of BBT thin films as dielectric layer for DRAM and integrated capacitor applications. ...
The typical measured small signal dielectric constant and dissipation factor, at 100 kHz, were 282 and 0.023, respectively, for films annealed at 700 ± C for 60 min. ...
Charge storage density as a function of applied electric field. the projected requirements for a DRAM cell capacitor with density beyond 64 Mbit.
IV. ...
doi:10.1557/jmr.1999.0250
fatcat:gepwr6yh5vfcbekol533xwmzdq
A low-noise folded bit-line sensing architecture for multigigabit DRAM with ultrahigh-density 6F/sup 2/ cell [CMOS design]
1998
IEEE Journal of Solid-State Circuits
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The 6F F F 2 cell is widely known for its small area, but its sensing is unstable due to the large array noises. ...
A new low-noise sensing scheme for a 6F F F 2 DRAM cell is proposed, employing two noise reduction methods: the divided sense and combined restore scheme and the bit-line noise absorbing scheme. ...
CONCLUSION A new low-noise sensing scheme for a cell arrangement is developed for a high-density cell in gigascale DRAM. ...
doi:10.1109/4.701271
fatcat:bjowc2cl6bcgffiqdelxowhicu
Understanding the Energy Consumption of Dynamic Random Access Memories
2010
2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
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Then the model is used together with assumptions about the DRAM roadmap to extrapolate DRAM energy consumption to future DRAM generations. ...
like increasing bandwidth requirements change DRAM energy consumption. ...
Mark Horowitz (Stanford University) and his colleagues at Rambus, especially Gary Bronner, Brent Haukness, Ely Tsern, Fred Ware and Brian Leibowitz for valuable discussions and suggestions. ...
doi:10.1109/micro.2010.42
dblp:conf/micro/Vogelsang10
fatcat:o6fwr22nbng2xfiuex45oxlcku
A capacitorless double-gate DRAM cell
2002
IEEE Electron Device Letters
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These characteristics suggest that a thin body, double-gate cell is an interesting candidate for high density DRAM technologies. ...
MEDICI simulations for 85 C show that a DG-DRAM cell may sustain a measurable change in drain current several hundred milliseconds after programming. ...
CONCLUSION DG-DRAM is intriguing for high density sub-100 nm DRAM technologies. ...
doi:10.1109/led.2002.1004230
fatcat:523mv3emxbacfhyq7bv7yrj4dm
A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache
2011
IEEE Journal of Solid-State Circuits
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and high density DRAM main memory. ...
Memories (DRAMs) density. ...
High-performance and high-density DRAM cache integration with high performance microprocessor has long been desired, because the embedded DRAM 3x density advantage and 1/5 of the keep-alive-power compared ...
doi:10.1109/jssc.2010.2084470
fatcat:zppa56cfivgz7hqanmbxnswqgy
0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability
2002
IEEE Journal of Solid-State Circuits
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Core size of 18.9 mm 2 and cell efficiency of 51.3% for the 32-Mb capacity, and core size of 33.4 mm 2 and cell efficiency of 58.1% for the 64-Mb capacity are realized. ...
This paper describes the 32-Mb and the 64-Mb embedded DRAM core with high efficient redundancy, which is fabricated using 0.13-m triple-well 4-level Cu embedded DRAM technology. ...
High cell efficiency compared to commodity DRAM of 51.3% at 32-Mb core and 58.1% at 64-Mb core is realized. Fig. 13 shows the measured shmoo plot of versus clock time (tCK) for the read cycle. ...
doi:10.1109/jssc.2002.1015693
fatcat:mnguu22ptzhzxomgqpzbqzjg3a
LOW POWER AND IMPROVED SPEED 1T DRAM USING DYNAMIC LOGIC
2018
Journal of Engineering Science and Technology
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The designed and proposed circuits are considered bypass logic and Boolean reduction technique that reduced number of transistors per designed cell logic. ...
This paper dealt with the design of 1-bit DRAM and efficient implementation of a sense amplifier. The proposed 1-bit DRAM designed using dynamic logic design. ...
The designed and proposed 3T DRAM is universally used by the advanced processor for on-chip data and program memory due to its high density and low cost of memory. ...
doaj:a07d54005daa4a408006f5dd12809c7a
fatcat:zxyqkadi6nfdzlaaulbmgckzie
The Umbrella Cell: A High-Density 2T Cell for SOC Applications
2005
IEICE transactions on electronics
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These results indicate that the umbrella cell is a strong candidate for providing a high-density memory for SOC applications. ...
To realize a high-density on-chip memory, the authors have proposed a novel logic-process-compatible memory cell. ...
Hiroyuki Mizuno, and Yusuke Kanno for their helpful comments and encouragement. ...
doi:10.1093/ietele/e88-c.4.614
fatcat:lr2cxplqwzc7hauh5d6rrqknjq
SIMULATION AND ANALYSIS OF 3T AND 4T CNTFET DRAM DESIGN IN 32nm TECHNOLOGY
2014
International Journal of Electronics Signals and Systems
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This paper presents 3TCNTFET & 4TCNTFET simulation and analysis of DRAM with metallic CNTFET using a CNTFET SPICE(HSPICE) model with 32ns technology have shown the DRAM cells in terms of leakage power, ...
Carbon Nanotube Field Effect Transistors (CNTFETs) is a promising device alternative for future nanometersscale technology. ...
ACKNOWLEDGMENT The authors would like to thank many people for useful discussions: Dr. S. ...
doi:10.47893/ijess.2014.1197
fatcat:27pyotkxcvdchnfibbpvd4a5cm
A 390-mm/sup 2/, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture
1999
IEEE Journal of Solid-State Circuits
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From 1987 to 1989, he worked on the circuit design and characterization of a 22-ns, 1-Mb CMOS high-speed DRAM with researchers and engineers at the IBM ...
These features result in a 1.6-Gb/s data rate for 2 2 232 200-MHz DDR operation with a cell/chip area efficiency of 67.5%. ...
Schulze for the layout of the 1-Gb DRAM. The authors would also like to thank the IBM/Siemens DRAM DDA integration team led by Dr. G. ...
doi:10.1109/4.799866
fatcat:zwrjvjrsibervcs5erg74bfn5m
1.1 TMACS/mW Fine-Grained Stochastic Resonant Charge-Recycling Array Processor
2012
IEEE Sensors Journal
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The 1 9 m 9 m 3T NMOS unit cell with a single-wire pitch multiplexed bit/compute line provides charge-conserving 1b-1b multiplication and single-node charge-domain analog accumulation. ...
We present a resonant adiabatic mixed-signal 128 256 array processor that achieves the energy efficiency of 1.1 TMACS (10 12 multiply accumulates per second) per mW of power operating from a 1.6 V DC supply ...
Fig. 11 . 11 Experimentally measured ML voltage as a function of A =A for the two cases of logic-one and logic-zero stored in all CID/DRAM cells. ...
doi:10.1109/jsen.2011.2113393
fatcat:7cjybqx5rjeefou2h2cugiwv3i
Embedded DRAM: Technology platform for the Blue Gene/L chip
2005
IBM Journal of Research and Development
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We also discuss the evolution of embedded DRAM technology into a higherperformance space in the 90-nm and 65-nm nodes and the potential for dynamic memory to improve overall memory subsystem performance ...
The IBM embedded DRAM platform allows this seamless integration without compromising performance, reliability, or yield. ...
Center line in East Fishkill, New York, for building the prototypes and early user hardware. ...
doi:10.1147/rd.492.0333
fatcat:feb76guwfzfobghzgtjwovcxke
A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM
1999
IEEE Journal of Solid-State Circuits
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DDR as a viable high-speed and low-voltage DRAM I/O interface is demonstrated. ...
A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-m process. ...
., Kyungki-Do, Korea, where he was engaged in DRAM design for 1 M, 4 M, low-voltage operated 16 M, SOI, and 1 G from 1985 to 1997. Since 1998, he has been working on the design of DDR SDRAM's. ...
doi:10.1109/4.799867
fatcat:f4rcevo3nzcgjlfdfh3t5rhile
CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off
[article]
2020
arXiv
pre-print
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density as a density-optimized commodity DRAM chip and 2) high-performance mode, where two adjacent DRAM cells in a DRAM row and their sense amplifiers are coupled to operate as a single low-latency logical ...
We believe that CLR-DRAM opens new research directions for a system to adapt to the diverse and dynamically changing memory capacity and access latency demands of workloads. ...
Acknowledgments We thank the anonymous ISCA 2020 reviewers for their feedback and the SAFARI group members for the stimulating intellectual environment they provide. ...
arXiv:2005.12775v1
fatcat:lj4fyi4ssjgldovtt3jebnd2fm
Architecting Optically-Controlled Phase Change Memory
[article]
2021
arXiv
pre-print
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These OPCM cells can be accessed directly with optical signals that are multiplexed in high-bandwidth-density silicon-photonic links. ...
Phase Change Memory (PCM) is an attractive candidate for main memory as it offers non-volatility and zero leakage power, while providing higher cell densities, longer data retention time, and higher capacity ...
access from the processor to a high-density memory. ...
arXiv:2107.11516v1
fatcat:eiouduid2jajjhdichyws56qly
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