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Architecture and Process Integration Overview of 3D NAND Flash Technologies

Geun Ho Lee, Sungmin Hwang, Junsu Yu, Hyungjin Kim
2021 Applied Sciences  
To overcome the scaling limit of planar NAND flash arrays, various three-dimensional (3D) architectures of NAND flash memory and their process integration methods have been investigated in both industry  ...  In this paper, 3D NAND flash technologies are reviewed in terms of their architecture and fabrication methods, and the advantages and disadvantages of the architectures are compared.  ...  Over time, the planar flash array has evolved into a 3D integrated architecture to increase memory capacity and overcome scaling issues.  ... 
doi:10.3390/app11156703 fatcat:usa2bsekoncqrh4oj622ekodea

Architectural and Integration Options for 3D NAND Flash Memories

Rino Micheloni, Luca Crippa, Cristian Zambelli, Piero Olivo
2017 Computers  
To keep the evolutionary pace of the technology, NAND Flash must scale aggressively in terms of bit cost.  ...  This review paper exposes several 3D NAND Flash memory technologies, along with their related integration challenges, by showing their different layouts, scaling trends and performance/reliability features  ...  The general scaling trend for every 3D NAND Flash technology is to increase the number of integrated layers.  ... 
doi:10.3390/computers6030027 fatcat:od6zyvkzafccrp75tkixkwynl4

Channel-Stacked NAND Flash Memory with High-κ Charge Trapping Layer for High Scalability

Joo Yun Seo, Yoon Kim, Sang-Ho Lee, Daewoong Kwon, Hee-Do Na, Hyun Chul Sohn, JongHo Lee, Byung-Gook Park
2019 2019 Electron Devices Technology and Manufacturing Conference (EDTM)  
For stacked NAND flash memory, the thickness of ONO (memory dielectric layers) will be a roadblock in scaling-down of the minimum feature size, while channel diameter can be scaled down to < 20 nm.  ...  Threedimensional (3D) NAND flash memory paved a new way of increasing the memory capacity by stacking cells in three-dimension.  ...  For stacked NAND flash memory, the thickness of ONO (memory dielectric layers) is a roadblock in scaling-down of the minimum feature size, because channel diameter can be scaled down to < 20 nm.  ... 
doi:10.1109/edtm.2019.8731328 fatcat:sc4eunm44bccffmfpzjfuplqea

Highly reliable, high speed and low power NAND flash memory-based Solid State Drives (SSDs)

Ken Takeuchi, Teruyoshi Hatanaka, Shuhei Tanakamaru
2012 IEICE Electronics Express  
A 56 nm CMOS 99 mm 2 8 Gb Multi-level NAND Flash Memory with 10 MB/s Program Throughput," Int.  ...  SSDs and emerging storage class non-volatile semiconductor memories such as PCRAM, FeRAM, RRAM and MRAM have enabled innovations in various nano-scale VLSI memory systems for personal computers, multimedia  ...  To overcome this problem, low power circuit technologies are proposed in [1] .  ... 
doi:10.1587/elex.9.779 fatcat:outxssmwz5fsdfijxe5tm4ehci

Review of Emerging New Solid-State Non-Volatile Memories

Yoshihisa Fujisaki
2013 Japanese Journal of Applied Physics  
Spin-transfer-torque MRAMs (STT-MRAMs) have been proposed as a solution to overcome the above-described problems of high operation current and unsuitability for scaling down.  ...  In addition, it is not difficult to build 3D memories such as BiCS flash with these binary-oxide ReRAMs. Moreover, 3D ReRAMs might have a simpler structure 100) than 3D flash memories.  ... 
doi:10.7567/jjap.52.040001 fatcat:m727uuw37bbulivxzyqp5garym

Monolithic 3D-ICs with single crystal silicon layers

Deepak C. Sekar, Zvi Or-Bach
2012 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International  
For a 140mm 2 die, the structure in Fig. 4 can provide 256Gbit chips compared with 64Gbit and 128Gbit for conventional scaled NAND and polysilicon-based 3D vertical NAND flash respectively [5].  ...  Monolithic 3D Memories Flash memory, which scales faster than logic and DRAM, may hit the limits of traditional scaling first.  ...  Fig. 4 : 4 Process Flow for monolithic 3D NAND flash with junctionfree charge-trap flash cells made of single crystal silicon. Ion-cut for transfer of un-patterned c-Si.  ... 
doi:10.1109/3dic.2012.6262978 dblp:conf/3dic/SekarO11 fatcat:fqbxans5wvhbpa6c2j3atw7g7y

Gate All around with Back Gate NAND Flash Structure for Excellent Reliability Characteristics in Program Operation

Jae-Min Sim, Bong-Seok Kim, In-Ho Nam, Yun-Heub Song
2021 Electronics  
A gate all around with back-gate (GAAB) structure was proposed for 3D NAND Flash memory technology.  ...  break down issue.  ...  Introduction In the memory market, 3D NAND flash memory is a mainstream technology that can achieve high bit density by increasing the mold stacking height [1] .  ... 
doi:10.3390/electronics10151828 fatcat:xccldkqixfesjev2nnygarzw3y

Efficient Numerical Schemes for Simulation and Optimization of Turbulent Reactive Flows [chapter]

J. Siegmann, G. Becker, J. Michaelis, M. Schäfer
2012 Fluid Mechanichs and its Application  
However, for many applications, NAND Flash read and write speeds are exceeding the capabilities of these legacy interconnects.  ...  to a platform's PCIe I/O interconnect.  ...  Nowadays, the most popular ECC approach in commercial SSDs is BCH, which is covered in Chap. 10. As the NAND technology scales down, NAND raw BER becomes worse and a more powerful ECC is needed.  ... 
doi:10.1007/978-94-007-5320-4_10 fatcat:hdu4r6bhcnbp3o3nmrncearqye

What Lies Ahead for Resistance-Based Memory Technologies?

Yoon-Jong Song, Gitae Jeong, In-Gyu Baek, Jungdal Choi
2013 Computer  
Recent work shows the feasibility of mass producing these new devices and their suitability for next-generation technology.  ...  Phase-change RAM, magnetic RAM, and resistive RAM offer strong scalability, speed, and power consumption advantages over conventional capacitance-based memory.  ...  These advantages make ReRAM a strong candidate to replace flash memory technology in such applications as code storage (NOR flash) and data storage (NAND).  ... 
doi:10.1109/mc.2013.221 fatcat:6y2oj55cabdphil3kgzglacxrm

State-of-the-art flash memory devices and post-flash emerging memories

ChihYuan Lu, HangTing Lue, YiChou Chen
2011 Science China Information Sciences  
We will then discuss various 3D memory architectures, technology challenges and address the poly-silicon thin film transistor (TFT) issues.  ...  Optimistically, 3D CT Flash memory may allow the density increase to continue for at least another decade beyond the 1Xnm node.  ...  The decoding architecture is a key issue in 3D NAND Flash design, and it also affects the cell scalability. Furthermore, the WL or BL sharing inevitably introduces more disturb issues.  ... 
doi:10.1007/s11432-011-4221-z fatcat:zpqszuxdlfc3pop6s6w6k7o5ly

Overview of candidate device technologies for storage-class memory

G. W. Burr, B. N. Kurdi, J. C. Scott, C. H. Lam, K. Gopalakrishnan, R. S. Shenoy
2008 IBM Journal of Research and Development  
The potential for practical scaling to ultrahigh effective areal density for each of these candidate technologies is then compared.  ...  We review the candidate solid-state nonvolatile memory technologies that potentially could be used to construct such an SCM.  ...  The introduction of NAND flash allowed a reduction in cell size from the 9-11 F 2 still used for NOR cells down to roughly 4 F 2 [2] .  ... 
doi:10.1147/rd.524.0449 fatcat:4wnf6cphxfgonisajdb4bghhxm

Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation [article]

Yixin Luo, Saugata Ghose, Yu Cai, Erich F. Haratsch, Onur Mutlu
2018 arXiv   pre-print
Compared to planar (i.e., two-dimensional) NAND flash memory, 3D NAND flash memory uses a new flash cell design, and vertically stacks dozens of silicon layers in a single chip.  ...  This allows 3D NAND flash memory to increase storage density using a much less aggressive manufacturing process technology than planar NAND flash memory.  ...  To overcome this scaling challenge, 3D NAND flash memory has recently been introduced [39, 45, 80] .  ... 
arXiv:1807.05140v2 fatcat:v276oedm6rexhdzmsdbkonx5qi

Executing real-time programs on negative-AND flash memory considering read disturb errors

Victoria Shangina, Kyoung-Soo We, Chang-Gun Lee
2017 2017 3rd IEEE International Conference on Computer and Communications (ICCC)  
More specifically, this research suggests a technique that will allow overcoming reliability issue of the embedded system that uses NAND flash memory for program execution.  ...  The relocation technique is invoked when the physical limit of read operations of NAND page -Thresholdis about to be reached.  ...  in January article "SSDs to become better & cheaper thanks to 3D NAND Flash" in Android Headlines states that in future due to the newly introduced technology, named 3D NAND, NAND flash memory may become  ... 
doi:10.1109/compcomm.2017.8323005 fatcat:r3yldczzhzdkdcvhyuinq6awme

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Alessandro Spinelli, Christian Compagnoni, Andrea Lacaita
2017 Computers  
We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field.  ...  A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.  ...  Acknowledgments: The authors would like to acknowledge Angelo Visconti, Paolo Tessariol, Emilio Camerlenghi and Akira Goda from Micron Technology Inc. for the fruitful and long-lasting collaboration, and  ... 
doi:10.3390/computers6020016 fatcat:63wprqy37jftxpavgau7pbtpra

Threshold voltage variation depending on single grain boundary and stored charges in an adjacent cell for vertical silicon–oxide–nitride–oxide–silicon NAND flash memory

Hyeongwan Oh, Jiwon Kim, Rock-Hyun Baek, Jeong-Soo Lee
2018 Japanese Journal of Applied Physics  
As the gate length is scaled down to 20 nm, the influence of stored charges in adjacent cells becomes significant, resulting in larger V th variations.  ...  In contrast, when the SGB is located at the center of the channel, the peak position of potential barrier is shifted to the center, so that the influence of the adjacent cell is diminished.  ...  Introduction To overcome the scaling limitations in the planar NAND flash architecture, the three-dimensional (3D) vertical NAND flash memory has been widely demonstrated.  ... 
doi:10.7567/jjap.57.04fe17 fatcat:ehupfugppvharbofop3yzfxsfy
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