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Case studies in determining the optimal field programmable gate array design for computing highly parallelisable problems

J.E. Rice, K.B. Kent
2009 IET Computers & Digital Techniques  
The optimal design on field programmable gate arrays (FPGAs) for problems with algorithms or sub-algorithms that can be highly parallelised is investigated.  ...  In each of these works only one particular type of problem was IET Comput.  ...  The advent of field programmable gate arrays (FPGAs) has provided researchers and industry alike with a hardware solution, leveraging much of the speed advantages of fabricated circuits that can be reprogrammed  ... 
doi:10.1049/iet-cdt.2008.0042 fatcat:bqtqgaxg7fdwfb2raqjk7uf7ju

The Durham ELT adaptive optics simulation platform [article]

Alastair Basden, Timothy Butterley, Richard Myers, Richard Wilson
2006 arXiv   pre-print
The simulation platform described here can be highly parallelised using parallelisation techniques suited for adaptive optics simulation, whilst still offering the user complete control while the simulation  ...  This platform is modular, object oriented and has the benefit of hardware application acceleration which can be used to improve the simulation performance, essential for ensuring that the run time of a  ...  The hardware accelerated algorithms are implemented within field programmable gate arrays (FPGAs), which can be programmed to provide impressive performance improvements over a standard software implementation  ... 
arXiv:astro-ph/0611294v1 fatcat:cfhjsybesze3nmwczoqkdypi2i

Quantum Accelerator Stack: A Research Roadmap [article]

K. Bertels, A. Sarkar, A. Krol, R. Budhrani, J. Samadi, E. Geoffroy, J. Matos, R. Abreu, G. Gielen, I. Ashraf
2021 arXiv   pre-print
In our case, the logic is expressed in the universal quantum-classical hybrid computation language developed in the group, called OpenQL.  ...  This paper presents the definition and implementation of a quantum computer architecture to enable creating a new computational device - a quantum computer as an accelerator In this paper, we present explicitly  ...  shown in Figure 1 , either field-programmable gate arrays (FPGA), graphics-processing units (GPU), neural processing units (NPU) like Google's tensor processing unit (TPU), etc.  ... 
arXiv:2102.02035v4 fatcat:vnbtwg2sq5etndxmjththyo5m4

Variational quantum algorithm with information sharing [article]

Chris N. Self, Kiran E. Khosla, Alistair W. R. Smith, Frederic Sauvage, Peter D. Haynes, Johannes Knolle, Florian Mintert, M. S. Kim
2021 arXiv   pre-print
This addresses a key challenge in scaling-up quantum algorithms towards demonstrating quantum advantage for problems of real-world interest.  ...  Our method solves related variational problems in parallel by exploiting the global nature of Bayesian optimisation and sharing information between different optimisers.  ...  However, in some cases simpler gates can be used (such as real valued Hamiltonians where R Y is sufficient).  ... 
arXiv:2103.16161v1 fatcat:bayjj6qsezdz3ghhbbciovdgre

A Survey on Agent-based Simulation using Hardware Accelerators [article]

Jiajian Xiao, Philipp Andelfinger, David Eckhoff, Wentong Cai, Alois Knoll
2018 arXiv   pre-print
To the best of our knowledge, no systematic overview of techniques for agent-based simulations on hardware accelerators has been given in the literature.  ...  Due to decelerating gains in single-core CPU performance, computationally expensive simulations are increasingly executed on highly parallel hardware platforms.  ...  Acknowledgement This work was financially supported by the Singapore National Research Foundation under its Campus for Research Excellence And Technological Enterprise (CREATE) programme.  ... 
arXiv:1807.01014v1 fatcat:dit3umjn4rddfiyifg6czcuaa4

A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation for Dense Matrices

Antonio Roldao, George A. Constantinides
2010 ACM Transactions on Reconfigurable Technology and Systems  
Recent developments in the capacity of modern Field Programmable Gate Arrays (FPGAs) have significantly expanded their applications.  ...  One such field is the acceleration of scientific computation and one type of calculation that is commonplace in scientific computation is the solution of systems of linear equations.  ...  Introduction With the increase in density and embedding of optimized multiplier blocks, modern Field Programmable Gate Arrays (FPGAs) have become increasingly suited for accelerating scientific computations  ... 
doi:10.1145/1661438.1661439 fatcat:ezsm6pvprnfefehkzvpj42fxyq

Customizable elliptic curve cryptosystems

R.C.C. Cheung, N.J. Telle, W. Luk, P.Y.K. Cheung
2005 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Index Terms-Field-programmable gate arrays (FPGAs), parallel architectures, public key cryptography, security.  ...  This paper presents a method for producing hardware designs for elliptic curve cryptography (ECC) systems over the finite field GF(2 ), using the optimal normal basis for the representation of numbers.  ...  ACKNOWLEDGMENT The authors thank the anonymous reviewers, and also P. Leong, D.-U. Lee, and A. A. Gaffar for their useful remarks and suggestions.  ... 
doi:10.1109/tvlsi.2005.857179 fatcat:jatcpxuo5zhnver5pdscjskzb4

Parallel Memetic Algorithm for VLSI Circuit Partitioning Problem using Graphical Processing Units

2012 Journal of Computer Science  
Here we used genetic algorithm to explore the search space and simulated annealing as a local search method to exploit the information in the search region for the optimization of VLSI netlist bi-Partitioning  ...  Program compilation, fitness case data and fitness execution are spread over the cores of GPU, allowing for the efficient processing of very large datasets.  ...  This study is concerned with the circuit partitioning problem. Circuit net list partitioning is an important step in VLSI physical design.  ... 
doi:10.3844/jcssp.2012.705.710 fatcat:hhxxbosirzbq3hurchx2hee4w4

Scalability and Validation of Big Data Bioinformatics Software

Andrian Yang, Michael Troup, Joshua W.K. Ho
2017 Computational and Structural Biotechnology Journal  
Software validation is the process of determining whether the program under test fulfils the task for which it was designed.  ...  Determining the correctness of the computational output of big data bioinformatics software is especially difficult due to the large input space and complex algorithms involved.  ...  Acknowledgements This work was supported in part by funds from the New South Wales Ministry of Health, a National Health and Medical Research Council/National Heart Foundation Career Development Fellowship  ... 
doi:10.1016/j.csbj.2017.07.002 pmid:28794828 pmcid:PMC5537105 fatcat:nnkrlwg35fd3hkpbg2jtosdicq

Evaluation of Clustering Algorithms on HPC Platforms

Juan M. Cebrian, Baldomero Imbernón, Jesús Soto, José M. Cecilia
2021 Mathematics  
In this paper, we evaluate different parallelisation strategies on different heterogeneous platforms for fuzzy clustering algorithms typically used in the state-of-the-art such as the Fuzzy C-means (FCM  ...  However, these algorithms are very computationally expensive as they often involve the computation of expensive fitness functions that must be evaluated for all points in the dataset.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/math9172156 fatcat:jtoovnt5vzej5g3ykhtwtpdlp4

Multi-Core Platform of Admittance Matrix Formation of Power Systems: Computational Time Assessment

Francisco Gonzalez-Longatt, Martha N. Acosta, Manuel Andrade, Ernesto Vazquez, Harold R. Chamorro, Vijay K. Sood
2020 2020 IEEE Electric Power and Energy Conference (EPEC)  
Results show the matrix approach considering sparse representation and parallel computing is the best approach in computing time.  ...  The algorithms have been implemented in MATLAB TM and tested in four multi-core platforms. Implementations include sparse and dense matrix representation and parallel/non-parallel computing.  ...  A Field Programmable Gate Array (FPGA) is a reconfigurable integrated circuit. The developer can configure the FPGA to become any circuit he/she wants to (as long as it fits on the FPGA).  ... 
doi:10.1109/epec48502.2020.9320060 fatcat:jvpcg66w6nfi5orcj3fxto4kkq

FPGA accelerator for machine learning interatomic potential based molecular dynamics of gold nanoparticles

Satya S. Bulusu, Srivathsan Vasudevan
2022 IEEE Access  
This work explores the concept of parallelization of the code and accelerating them by exploring the usage of high level synthesis (HLS) based Field Programmable Gate Array (FPGA).  ...  The scientific community is dependent on high-end servers for such computations that are generally sequential and highly power hungry, thereby restricting these computations in reaching experimentally  ...  They also thank IIT Indore for providing the server facilities -OMICORN [GenuineIntel 2600.0 MHz].  ... 
doi:10.1109/access.2022.3165650 fatcat:pgt4w2cugjhdjjibn54nd7px2a

Type-Driven Automated Program Transformations and Cost Modelling for Optimising Streaming Programs on FPGAs

Wim Vanderbauwhede, Syed Waqar Nabi, Cristian Urlea
2018 International journal of parallel programming  
We target streaming programs for the problem domain of scientific computing, such as numerical weather prediction.  ...  In this paper we present a novel approach to program optimisation based on compiler-based type-driven program transformations and a fast and accurate cost/performance model for the target architecture.  ...  Acknowledgements The authors acknowledge the support of the UK EPSRC for the TyTra project (EP/L00058X/1). Open Access  ... 
doi:10.1007/s10766-018-0572-z fatcat:gqqcbzbqabg2vhrqcftgoo67qq

On the impact of quantum computing technology on future developments in high-performance scientific computing

Matthias Möller, Cornelis Vuik
2017 Ethics and Information Technology  
In this article we describe our vision of future developments in scientific computing that would be enabled by the advent of software-programmable quantum computers.  ...  Building a quantum computer that can be used practically is in itself an outstanding challenge that has become the 'new race to the moon'.  ...  A new trend in scientific computing that aims at overcoming the memory-processor communication bottleneck is the rediscovery of reconfigurable hardware, e.g., field programmable gate arrays.  ... 
doi:10.1007/s10676-017-9438-0 fatcat:24xndp2mj5gazmdcphgbpbgtme

Efficient reconfigurable architectures for 3D medical image compression

Afandi Ahmad, Abbes Amira
2009 2009 International Conference on Field-Programmable Technology  
Reconfigurable hardware, in the form of field programmable gate arrays (FPGAs) has been proposed as viable system building block in the construction of high-performance systems at an economical price.  ...  An evaluation of the 3-D integer transform (IT) and the discrete wavelet transform (DWT) with lifting scheme (LS) for transform blocks reveal that 3-D IT demonstrates better computational complexity than  ...  In particular, I would like to thank my supervisor, Dr Abbes Amira, for accepting me as a student, whilst I am in a dark tunnel. Abbes,  ... 
doi:10.1109/fpt.2009.5377682 fatcat:uynxh2ce2rfqtoiktcqqqcnyie
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