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Call Paths for Pin Tools

Milind Chabbi, Xu Liu, John Mellor-Crummey
2014 Proceedings of Annual IEEE/ACM International Symposium on Code Generation and Optimization  
is expensive (both memory and time) • CCTLib ✦ Provides calling context for Pin tools ✦ Achieves ubiquitous code-and data-centric attribution via appropriate choice of algorithms and data structures process  ...  Time overhead for call stack unwinding at each memory access 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 shadow memory shadow memory Frameworks for Fine-Grained Program Monitoring "Getting calling contexts  ... 
doi:10.1145/2544137.2544164 fatcat:sjxxwbjjcbdk3evmxupuhsvezq

Controlling program execution through binary instrumentation

Heidi Pan, Krste Asanović, Robert Cohn, Chi-Keung Luk
2005 SIGARCH Computer Architecture News  
This paper introduces some simple and general mechanisms for a binary instrumentation infrastructure to provide control over the application's execution path, allowing tools to replay or skip parts of  ...  Binary instrumentation has been widely used to observe dynamic program behavior, but current binary instrumentation systems do not allow the tool writer to alter the program execution path.  ...  The tool then resumes in place by either calling PIN Resume or PIN ExecuteAt using the respective IARG.  ... 
doi:10.1145/1127577.1127587 fatcat:atffdlpenrehzp5nw5ekds6pci

Pinpointing data locality bottlenecks with low overhead

Xu Liu, John Mellor-Crummey
2013 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)  
In this paper, we describe a novel, efficient, and effective tool for data locality measurement and analysis.  ...  Our tool identifies data touched by reuse pairs and the accesses involved, identified with their full calling context.  ...  ACKNOWLEDGEMENTS We would like to thank the reviewers for their feedback about how to improve the paper. We especially thank the reviewer who helped us improve the related work section.  ... 
doi:10.1109/ispass.2013.6557169 dblp:conf/ispass/LiuM13 fatcat:sehyf7issre7ral7ekn7hs6yke

Timing- and constraint-oriented placement for interconnected LSIs in mainframe design

Yasushi Ogawa, Tsutomu Itoh, Yoshio Miki, Tatsuki Ishii, Yasuo Sato, Reiji Toyoshima
1991 Proceedings of the 28th conference on ACM/IEEE design automation conference - DAC '91  
Hierarchical pin assignment, timing-driven placement, and high speed and precision timing analysis are proposed for achieving the above goals.  ...  Such algorithms are applied to a physical hierarchy containing 12 thousand gate ECL gate-array LSIs for the Hitachi M-880, a newly developed high-end mainframe computer.  ...  Hidekazu Terai and Tokinori Kozawa for many useful discussions and comments.  ... 
doi:10.1145/127601.127676 dblp:conf/dac/OgawaIMIST91 fatcat:cgfyovaprrcibnrq3ke6q5u6eu

IOPin: Runtime Profiling of Parallel I/O in HPC Systems

Seong Jo Kim, Seung Woo Son, Wei-keng Liao, Mahmut Kandemir, Rajeev Thakur, Alok Choudhary
2012 2012 SC Companion: High Performance Computing, Networking Storage and Analysis  
For the I/O software developers, ensuring data flow is important among these software layers with performance close to the hardware limits.  ...  The goal of Pin is to provide an instrumentation platform for implementing a variety of program analysis tools for multiple architectures.  ...  Motivated by these observations, we have developed a dynamic performance visualization and analysis tool for parallel I/O, called IOPin.  ... 
doi:10.1109/sc.companion.2012.14 dblp:conf/sc/KimSLKTC12 fatcat:ucoeziowqzhafc5fpll2bhatpy

Page 36 of Manufacturing Engineering Vol. 21, Issue 1 [page]

1948 Manufacturing Engineering  
Tool for Oil Grooving \ LARGE orpdER which called for oil grooves running con tinuously from the top of the flange and down along the 1.1).. on large powder metal bushings presented an acute tooling problem  ...  When loading and unloading, the head is raised clear of the fixture and guided by wavs at tached to the drill column: thus, the guide pin enters the cam path on the down travel of the spindle With the  ... 

Depth First Always On Routing Trace Algorithm [article]

Anthony Kim, Sung Hyun Chen, Chen Zheng
2017 arXiv   pre-print
In this paper, we discussed current limitation in the electronic-design-automotation (EDA) tool on tracing the always on routing.  ...  The problem is formulated below: for all AON instances, find its current path from its secondary power pin to the VDD supply tapping point and estimate the total voltage drop along the path.  ...  Conclusions In this paper we show the limitation of current EDA tool to provide trace check for AON routings.  ... 
arXiv:1711.04172v1 fatcat:r5fklwno7jctdf344bexwlypmi

Quark Routing [chapter]

Sean T. McCulloch, James P. Cohoon
2003 Lecture Notes in Computer Science  
With inherent problem complexity, ever increasing instance size and ever decreasing layout area, there is need in physical design for improved heuristics and algorithms.  ...  We call this version QUARK-PRIME. QUARK-PRIME required several minutes to produce its solution for the smaller instances.  ...  We call these local decision processes the net's personality.  ... 
doi:10.1007/978-3-540-45234-8_14 fatcat:fqryqe7fqzdhlphy22jrmcwqd4

A hybrid complete-graph partial-crossbar routing architecture for multi-FPGA systems

Mohammed A. S. Khalid, Jonathan Rose
1998 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays - FPGA '98  
Furthermore, the critical path delay for designs implemented on the partial crossbar increased, and were on average 9% more than the HCGP architecture and up to 26% more.  ...  A customized set of partitioning and inter-chip routing tools were developed, with particular attention paid to architectureappropriate inter-chip routing algorithms.  ...  Acknowledgments The authors would like to thank Dave Galloway for his help with the partitioning tool and Jason Anderson for his help in synthesizing the benchmark circuits.  ... 
doi:10.1145/275107.275119 dblp:conf/fpga/KhalidR98 fatcat:eidx2fxedze3rfozebr2r5iqli

Identifying potential parallelism via loop-centric profiling

Tipp Moseley, Daniel A. Connors, Dirk Grunwald, Ramesh Peri
2007 Proceedings of the 4th international conference on Computing frontiers - CF '07  
The paper concludes with a case study evaluating the tool on several SPEC 2000 benchmarks.  ...  Outer loops are relatively easy targets for parallelization, but traditional profilers focus primarily on functions and hot inner loops.  ...  To validate their results, a full path profile was gathered using a Pin tool.  ... 
doi:10.1145/1242531.1242554 dblp:conf/cf/MoseleyCGP07 fatcat:tutgvmwu2vdi7b5mfwzekpcyyi

Research on Net Weighting Schemes in Performance Driven Global Routing

2019 International journal of recent technology and engineering  
We investigate four methods for weighting the critical nets during performance driven global routing.  ...  This paper presents a comparative study conducted on the four methods for net weighting proposed by us in our previous works  ...  ACKNOWLEDGEMENTS We would like to thank Department of Electronics and Communication Engineering, Cambridge Institute of Technology, Bangalore for providing the resources to conduct the experiments.  ... 
doi:10.35940/ijrte.b1212.0782s319 fatcat:gcur6iwn5rgrfjxdpvnctyhkxu

Test development for second-generation ColdFire microprocessors

D. Amason, A.L. Crouch, R. Eisele, G. Giles, M. Mateja
1998 IEEE Design & Test of Computers  
The scan vectors used for AC purposes-that is, for timing specification measurements-were generated using the path delay fault model.  ...  To minimize the number of pins dedicated to test, they arranged for the scan ports of these multiple scan chains to be shared with functional pins.  ...  Acknowledgments We thank the ColdFire microprocessor design and product engineering teams for their contributions to this work, and we thank Matthew Pressly, specifically, for his participation.  ... 
doi:10.1109/54.706036 fatcat:wxlpxssoobesrdihcngbutjeje

Integrating hardware and software information flow analyses

Colin J. Fidge, Diane Corney
2009 Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems - LCTES '09  
This is done by unifying input/output statements in embedded program execution paths with the hardware pins they access, and by associating significant software states with corresponding operating modes  ...  This process includes tracing potential information flow through the device's electronic circuitry, for each of the device's operating modes.  ...  We wish to thank Brian Palm, Vicky Briant and Peter Young for their ongoing support for this research, and the anonymous reviewers for their helpful comments.  ... 
doi:10.1145/1542452.1542474 dblp:conf/lctrts/FidgeC09 fatcat:mn77mmroobcglnrf2gtowvoezu

Integrating hardware and software information flow analyses

Colin J. Fidge, Diane Corney
2009 SIGPLAN notices  
This is done by unifying input/output statements in embedded program execution paths with the hardware pins they access, and by associating significant software states with corresponding operating modes  ...  This process includes tracing potential information flow through the device's electronic circuitry, for each of the device's operating modes.  ...  We wish to thank Brian Palm, Vicky Briant and Peter Young for their ongoing support for this research, and the anonymous reviewers for their helpful comments.  ... 
doi:10.1145/1543136.1542474 fatcat:hgijkszf3jhqfjltrukkftthxq

The Taint Rabbit: Optimizing Generic Taint Analysis with Dynamic Fast Path Generation

John Galea, Daniel Kroening
2020 Proceedings of the 15th ACM Asia Conference on Computer and Communications Security  
In this paper, we explore the hypothesis whether just-in-time (JIT) generation of fast paths for tracking taint can enhance the performance.  ...  For instance, Dytan incurs an average overhead of 237x, while the Taint Rabbit achieves 1.7x on the same set of benchmarks.  ...  We also thank the researchers of other taint engines for making their tools available, and the anonymous reviewers for their invaluable feedback.  ... 
doi:10.1145/3320269.3384764 dblp:conf/ccs/GaleaK20 fatcat:nzsmwzdp4jh6vglaxtghfduqky
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