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A Survey on Static Cache Analysis for Real-Time Systems

Mingsong Lv, Nan Guan, Jan Reineke, Reinhard Wilhelm, Wang Yi
2015 Leibniz Transactions on Embedded Systems  
Then, the discussion is extended to cache analysis in complex execution environment, followed by a survey of existing tools based on static techniques for cache analysis.  ...  We first present the challenges and static analysis techniques for independent programs with respect to different cache features.  ...  The extra delay due to cache reloading is commonly referred to as the Cache-Related Preemption Delay (CRPD).  ... 
doi:10.4230/lites-v003-i001-a005 dblp:journals/lites/LvGRW016 fatcat:ax5h3hurpbekjo52thkaduwtki

NPM-BUNDLE: Non-Preemptive Multitask Scheduling for Jobs with BUNDLE-Based Thread-Level Scheduling

Corey Tessler, Nathan Fisher, Michael Wagner
2019 Euromicro Conference on Real-Time Systems  
The BUNDLE and BUNDLEP scheduling algorithms are cache-cognizant thread-level scheduling algorithms and associated worst case execution time and cache overhead (WCETO) techniques for hard real-time multi-threaded  ...  This thread-level preemption is a requirement for the run-time behavior and WCETO calculation to receive the benefit of BUNDLE-based approaches.  ...  Introduction Hard real-time multi-threaded task systems which incorporate cache memory, must account for the variation in execution time and cache related preemption delays found in singlethreaded task  ... 
doi:10.4230/lipics.ecrts.2019.15 dblp:conf/ecrts/TesslerF19 fatcat:u6vrzeqf2nelfkh3esukrl5ksq

Timing analysis of concurrent programs running on shared cache multi-cores

Yun Liang, Huping Ding, Tulika Mitra, Abhik Roychoudhury, Yan Li, Vivy Suhendra
2012 Real-time systems  
In this paper, we develop a timing analysis method for concurrent software running on multi-cores with a shared instruction cache.  ...  Timing analysis of real-time embedded software thus requires bounding the time for memory accesses.  ...  For preemptive systems, we need to include cache-related preemption delay analysis ( [9] , [22] , [15] , [18] ) in our framework.  ... 
doi:10.1007/s11241-012-9160-2 fatcat:2qo6lo2vbfbujovtanzegdam6e

Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores

Yan Li, Vivy Suhendra, Yun Liang, Tulika Mitra, Abhik Roychoudhury
2009 2009 30th IEEE Real-Time Systems Symposium  
In this paper, we develop a timing analysis method for concurrent software running on multi-cores with a shared instruction cache.  ...  Timing analysis of real-time embedded software thus requires bounding the time for memory accesses.  ...  For preemptive systems, we need to include cache-related preemption delay analysis ( [9] , [22] , [15] , [18] ) in our framework.  ... 
doi:10.1109/rtss.2009.32 dblp:conf/rtss/LiSLMR09 fatcat:h7jodlkpkfgxlggaob4cwqgvxi

WCET analysis of instruction cache hierarchies

Damien Hardy, Isabelle Puaut
2011 Journal of systems architecture  
In this paper, we propose a safe static instruction cache analysis method for multi-level caches.  ...  Variations of the method are presented to model different cache hierarchy management policies between cache levels: non-inclusive, inclusive and exclusive cache hierarchies.  ...  We also wish to thank Benjamin Lesage for his help concerning the analysis of exclusive cache hierarchies, and Jan Reineke for his comments about the mls and evict bounds used to model non-LRU cache replacement  ... 
doi:10.1016/j.sysarc.2010.08.007 fatcat:rw2vm7ohvvhfrli32xtok2itvu

Improved cache related pre-emption delay aware response time analysis for fixed priority pre-emptive systems

Sebastian Altmeyer, Robert I. Davis, Claire Maiza
2012 Real-time systems  
In such systems, cache related pre-emption delays can be a significant proportion of task execution times.  ...  A case study and empirical evaluation demonstrate the effectiveness of the ECB-Union, Multiset and combined approaches for a wide range of different cache configurations including cache utilization, cache  ...  We also like to thank Alan Burns, Jack Whitham and the anonymous reviewers for their comments on an earlier draft of this paper.  ... 
doi:10.1007/s11241-012-9152-2 fatcat:t6k3okbv2fhlbkocvzm62ho5nq

Message from the Workshop Chair

2005 2005 International Conference on Cyberworlds (CW'05)  
related to object oriented programming models. ¡ On low-level analysis techniques the focus is on modelling timing behaviour of processor features such as cache effects, branch prediction and speculative  ...  The aim of the workshop is to provide a forum for discussing current trends and issues related to the timing analysis of Real-Time Systems with special emphasis on bridging the gap between industry and  ...  I would like to thank the anonymous reviewers for their helpful comments and the workshop participants for their comments during insightful discussions.  ... 
doi:10.1109/cw.2005.66 dblp:conf/cw/XX05a fatcat:ubjg3eboa5cojl5mrrgucd42ae

Towards Predictable Real-Time Performance on Multi-Core Platforms [article]

Hyoseung Kim
2016 arXiv   pre-print
such as caches, memory buses, and I/O devices.  ...  Specifically, we tackle the issues of cache and memory contention, locking and synchronization, interrupt handling, and access control for computational accelerators such as GPGPUs, all of which are crucial  ...  preemption delay due to τ h . τ l also has one cache warm-up delay and one cache-related preemption delay.  ... 
arXiv:1607.08578v1 fatcat:2ndmimzpxbehzlntoppabtusbq


Yinqian Zhang, Michael K. Reiter
2013 Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security - CCS '13  
Düppel includes defenses for timeshared caches such as per-core L1 and L2 caches.  ...  This paper presents the design, implementation and evaluation of a system called Düppel that enables a tenant virtual machine to defend itself from cache-based side-channel attacks in public clouds.  ...  Weidong Cui and the anonymous reviewers for suggestions that led to improvements to this paper.  ... 
doi:10.1145/2508859.2516741 dblp:conf/ccs/ZhangR13 fatcat:axty5jofjncqdljxz6cxgasa6m

Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches

Damien Har, Thomas Piquet, Isabelle Puaut
2009 2009 30th IEEE Real-Time Systems Symposium  
Estimating WCETs for multi-core platforms is very challenging because of the possible interferences between cores due to shared hardware resources such as shared caches, memory bus, etc.  ...  For real-time systems to exploit multi-core architectures, it is required to obtain both tight and safe estimates of worst-case execution times (WCETs).  ...  The computation of cache-related preemption delay due to intra-core interferences is considered out of the scope of this paper.  ... 
doi:10.1109/rtss.2009.34 dblp:conf/rtss/HardyPP09 fatcat:4spi7ls7yzbatlinmfnhm7u24y

Modeling shared cache and bus in multi-cores for timing analysis

Sudipta Chattopadhyay, Abhik Roychoudhury, Tulika Mitra
2010 Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems - SCOPES '10  
The key to solving this problem is to accurately model the timing effects of shared resources in multi-cores, namely shared cache and bus.  ...  In this paper, we provide an integrated timing analysis framework that captures timing effects of both shared cache and shared bus.  ...  For multi-tasking systems, cache analysis estimates the cache-related preemption delay (CRPD).  ... 
doi:10.1145/1811212.1811220 dblp:conf/scopes/ChattopadhyayRM10 fatcat:tixgfywtlvhp5g5gckrzg5aoci

A Power-Aware Multi-Level Cache Organization Effective for Multi-Core Embedded Systems

Abu Asaduzzaman
2013 Journal of Computers  
Cache-level miss table holds information about the memory blocks that cause most level-1 cache (CL1) misses under normal execution.  ...  Proposed cache organization also includes private victim caches (VCs) to hold level-1 victim blocks and shared level-2 cache (CL2) to help synchronization.  ...  According to these approaches, cache contents are statically locked so as to make memory access time and cache-related preemption delay predictable.  ... 
doi:10.4304/jcp.8.1.49-60 fatcat:q3up32fvv5bl5koomlhfxjf6ky

The Last Mile

David Cock, Qian Ge, Toby Murray, Gernot Heiser
2014 Proceedings of the 2014 ACM SIGSAC Conference on Computer and Communications Security - CCS '14  
We perform such an analysis, collecting a large data set (2,000 hours of observations) for two representative timing channels, the locally-exploitable cache channel and a remote exploit of OpenSSL execution  ...  Timing channels remain the last mile for confidentiality and are still beyond the reach of formal analysis, so must be dealt with empirically.  ...  As the caches on this chip are inclusive, this also evicts kernel code for the sender's domain.  ... 
doi:10.1145/2660267.2660294 dblp:conf/ccs/CockGMH14 fatcat:jnl7bomsfjh5zntliagbwyepyi

WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches

Damien Hardy, Isabelle Puaut
2008 2008 Real-Time Systems Symposium  
Centre de recherche INRIA Rennes -Bretagne Atlantique IRISA, Campus universitaire de Beaulieu, 35042 Rennes Cedex Téléphone : +33 2 99 84 71 00 -Télécopie : +33 2 99 84 71 71 WCET analysis of multi-level  ...  To the best of our knowledge, there is only one approach for WCET estimation for systems with cache hierarchies [10], which turns out to be unsafe for setassociative caches.  ...  The impact of multi-tasking has also been considered by approaches aiming at statically determining cache related preemption delays [12, 17] .  ... 
doi:10.1109/rtss.2008.10 dblp:conf/rtss/HardyP08 fatcat:szdmelzcl5fhjida34ubdyya3u

Memory Access Control in Multiprocessor for Real-Time Systems with Mixed Criticality

Heechul Yun, Gang Yao, Rodolfo Pellizzoni, Marco Caccamo, Lui Sha
2012 2012 24th Euromicro Conference on Real-Time Systems  
ACKNOWLEDGEMENTS We thank the anonymous reviewers for useful feedback that improved the quality of this paper.  ...  [17] developed a response time analysis for COTS based multi-core systems.  ...  We assume preemption does not affect the number of cache-misses of a task, for example by partitioning cache to each task.  ... 
doi:10.1109/ecrts.2012.32 dblp:conf/ecrts/YunYPCS12 fatcat:yikdsyudqvaydmulcfnkree37m
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