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PI : a Parallel in-memory skip list based Index [article]

Zhongle Xie, Qingchao Cai, H.V. Jagadish, Beng Chin Ooi, Weng-Fai Wong
2016 arXiv   pre-print
will be modified as a result of query processing will be accessed by exactly one thread.  ...  In this paper, we present PI, a Parallel in-memory skip list based Index that lends itself naturally to the parallel and concurrent environment, particularly with non-uniform memory access.  ...  propose new skip list algorithms [14] to avoid contention on hot spots. Abraham et al. combine skip lists and B-trees for efficient query processing [2] .  ... 
arXiv:1601.00159v1 fatcat:qe56jjavszhr3am65dbvkedqgq

Skewed partial bitvectors for list intersection

Andrew Kane, Frank Wm. Tompa
2014 Proceedings of the 37th international ACM SIGIR conference on Research & development in information retrieval - SIGIR '14  
Even though byte aligned operations are fast, there are many if statements in the code, which can slow down execution on modern CPUs.  ...  ., loading from memory into CPU cache) can be a large portion of the runtime cost of a query.  ... 
doi:10.1145/2600428.2609609 dblp:conf/sigir/KaneT14 fatcat:fuwxdwf7x5cd7mie277owhkdt4

Fluid Co-processing

Tim Gubner, Diego Tomé, Harald Lang, Peter Boncz
2019 Proceedings of the 15th International Workshop on Data Management on New Hardware - DaMoN'19  
The next quest is for a database architecture that allows efficient CPU-GPU co-processing. We present a new heterogeneous query processing framework based on fluid coprocessing.  ...  Our microbenchmarks show that raw Bloom filter lookups are up to 6× faster on the GPU than on the CPU in case the Bloom filter is larger than the CPU cache.  ...  Our microbenchmarks show that raw Bloom filter lookups are up to 6× faster on the GPU than on the CPU in case the Bloom filter is larger than the CPU cache (skip to Figure 3 ).  ... 
doi:10.1145/3329785.3329934 dblp:conf/damon/GubnerTLB19 fatcat:vpdrxtcmxraffjjkhbpn5i4upi

A Comparison of Document-at-a-Time and Score-at-a-Time Query Evaluation

Matt Crane, J. Shane Culpepper, Jimmy Lin, Joel Mackenzie, Andrew Trotman
2017 Proceedings of the Tenth ACM International Conference on Web Search and Data Mining - WSDM '17  
Furthermore, JASS query latency is not particularly sensitive to the retrieval depth, making it an appealing solution for performance-sensitive applications where bounds on query latencies are desirable  ...  Surprisingly, approximate query evaluation in WAND and BMW does not significantly reduce the risk of these tail queries.  ...  Skipping, however, has associated costs that may be non-trivial on modern processor architectures.  ... 
doi:10.1145/3018661.3018726 dblp:conf/wsdm/CraneCLMT17 fatcat:reo2etfwwvhddaqbjirg4av4nq

Efficient Inner Product Approximation in Hybrid Spaces [article]

Xiang Wu, Ruiqi Guo, David Simcha, Dave Dopson, Sanjiv Kumar
2019 arXiv   pre-print
We also propose efficient data structures that exploit modern computer architectures, resulting in orders of magnitude faster search than the existing baselines.  ...  Popular techniques like Locality Sensitive Hashing (LSH) and its data-dependent variants also do not give good accuracy in high dimensional hybrid spaces.  ...  an issue with modern CPUs.  ... 
arXiv:1903.08690v1 fatcat:4yhxsdp7l5ecjekthkbloc4b2u

In-Memory Big Data Management and Processing: A Survey

Hao Zhang, Gang Chen, Beng Chin Ooi, Kian-Lee Tan, Meihui Zhang
2015 IEEE Transactions on Knowledge and Data Engineering  
Many of these researches have focused along several dimensions: modern CPU and memory hierarchy utilization, time/space efficiency, parallelism and concurrency control.  ...  However, in-memory systems are much more sensitive to other sources of overhead that do not matter in traditional I/O-bounded disk-based systems.  ...  Moreover, the protocol should be data-locality sensitive and cache aware, which matter more for modern machines [187] . • Query processing.  ... 
doi:10.1109/tkde.2015.2427795 fatcat:u7r3rtvhxbainfeazfduxcdwrm

Accelerating In-Memory Database Selections Using Latency Masking Hardware Threads

Prerna Budhkar, Ildar Absalyamov, Vasileios Zois, Skyler Windh, Walid A. Najjar, Vassilis J. Tsotras
2019 ACM Transactions on Architecture and Code Optimization (TACO)  
This accelerator focuses on the range-partitioning step of query processing to insure that each partition can fit on an on-chip cache.  ...  Fig. 18 . 18 Comparison of power efficiency on MTP, CPU, and GPU systems.  ... 
doi:10.1145/3310229 fatcat:g4zabsnadfbt5kdmfn5c7tqb2e

Reducing the Storage Overhead of Main-Memory OLTP Databases with Hybrid Indexes

Huanchen Zhang, David G. Andersen, Andrew Pavlo, Michael Kaminsky, Lin Ma, Rui Shen
2016 Proceedings of the 2016 International Conference on Management of Data - SIGMOD '16  
Using indexes for query execution is crucial for achieving high performance in modern on-line transaction processing databases.  ...  Our first contribution is hybrid index, a dual-stage index architecture that achieves both space efficiency and high performance.  ...  Skip List … … … … … … … … … … … … Node Cache ART … … key pointer/ value … … … … Node Cache … … Table 2 : 2 Point Query Profiling -CPU-level profiling  ... 
doi:10.1145/2882903.2915222 dblp:conf/sigmod/ZhangAPKMS16 fatcat:rh4qexnquvfolddctr3fqory44

The adaptive radix tree: ARTful indexing for main-memory databases

V. Leis, Alfons Kemper, T. Neumann
2013 2013 IEEE 29th International Conference on Data Engineering (ICDE)  
Traditional in-memory data structures like balanced binary search trees are not efficient on modern hardware, because they do not optimally utilize on-CPU caches.  ...  Hash tables, also often used for main-memory indexes, are fast but only support point queries.  ...  Caching Effects Let us now investigate caching effects. For modern CPUs, caches are extremely important, because DRAM latency amounts to hundreds of CPU cycles.  ... 
doi:10.1109/icde.2013.6544812 dblp:conf/icde/LeisK013 fatcat:sma67ydio5c5vpuok4axiruanu

Optimizing Burrows-Wheeler Transform-Based Sequence Alignment on Multicore Architectures

Jing Zhang, Heshan Lin, Pavan Balaji, Wu-Chun Feng
2013 2013 13th IEEE/ACM International Symposium on Cluster, Cloud, and Grid Computing  
We then propose a locality-aware implementation of BWA that aims at optimizing its performance by better exploiting the caching mechanisms of modern multicore processors.  ...  Through an in-depth performance analysis of BWA, a popular BWT-based aligner on multicore architectures, we demonstrate that such tools are limited by memory bandwidth due to their irregular memory access  ...  Our paper, on the other hand, focuses on optimizing BWT-based alignment on multicore CPUs by remapping the algorithm to better exploit the caching mechanism of modern processors.  ... 
doi:10.1109/ccgrid.2013.67 dblp:conf/ccgrid/ZhangLBF13 fatcat:6olzfr37wfcjvp62vboodprqfa

A Survey of GPU-Based Large-Scale Volume Visualization [article]

Johanna Beyer, Markus Hadwiger, Hanspeter Pfister
2014 Eurographics Conference on Visualization  
Modern techniques in this field have brought about a sea change in how interactive visualization and analysis of giga-, tera-, and petabytes of volume data can be enabled on GPUs.  ...  screen, i.e., "output-sensitive" algorithms and system designs.  ...  visibility by employing efficient read-back mechanisms from the GPU to the CPU.  ... 
doi:10.2312/eurovisstar.20141175 dblp:conf/vissym/BeyerHP14 fatcat:7bxd7zifyba37nqkcuht3qtsxy

An Efficient SSD-based Hybrid Storage Architecture for Large-Scale Search Engines

Ruixuan Li, Chengzhou Li, Weijun Xiao, Hai Jin, Heng He, Xiwu Gu, Kunmei Wen, Zhiyong Xu
2012 2012 41st International Conference on Parallel Processing  
Caching is an effective optimization, and many caching algorithms have been proposed to improve retrieval performance.  ...  We analyze the I/O patterns of search engines and propose SSD-based data management policies based on the hybrid storage architecture, including data selection, data placement and data replacement.  ...  Second, the results are prominently relevant to the queries and time-sensitive, while the inverted lists are relatively stable.  ... 
doi:10.1109/icpp.2012.17 dblp:conf/icpp/LiLXJHGWX12 fatcat:yqw4exfejbbhrakjnko725dkfi

Cache Design of SSD-Based Search Engine Architectures

Jianguo Wang, Eric Lo, Man Lung Yiu, Jiancong Tong, Gang Wang, Xiaoguang Liu
2014 ACM Transactions on Information Systems  
Based on the results, we give insights to practitioners and researchers on how to adapt the infrastructure and caching policies for SSD-based search engines.  ...  In this article, we carry out a series of empirical experiments to study the impact of SSD on search engine cache management.  ...  Furthermore, since both random reads and sequential reads are fast on SSD while query processing in modern search engines involves several CPU-intensive steps (e.g., query result ranking [Turtle and Flood  ... 
doi:10.1145/2661629 fatcat:7vrj25m45ra35nc5rhwsfm6oau

Efficient Query Processing for Scalable Web Search

Nicola Tonellotto, Craig Macdonald, Iadh Ounis
2018 Foundations and Trends in Information Retrieval  
the latest trends in the literature in efficient query processing, including the coherent and systematic reviews of techniques such as dynamic pruning and impact-sorted posting lists as well as their variants  ...  Finally, the survey concludes with a summary of open directions in efficient search infrastructures, namely the use of signatures, real-time, energy-efficient and modern hardware & software architectures  ...  Dimopoulos et al. (2013a) illustrated an optimised implementation of docid-oriented blockmax indexes exploiting the SIMD processing capabilities of modern CPUs and adhoc caching policies.  ... 
doi:10.1561/1500000057 fatcat:wx53qhvfhnfwfc4hgdva5ypw3u

The Bw-Tree: A B-tree for new hardware platforms

J. J. Levandoski, D. B. Lomet, S. Sengupta
2013 2013 IEEE 29th International Conference on Data Engineering (ICDE)  
Our new form of B-tree, called the Bw-tree achieves its very high performance via a latch-free approach that effectively exploits the processor caches of modern multi-core chips.  ...  This paper describes the architecture and algorithms for the Bw-tree, focusing on the main memory aspects.  ...  Cache Performance This experiment measures the CPU cache efficiency of the Bw-tree compared to the skip list.  ... 
doi:10.1109/icde.2013.6544834 dblp:conf/icde/LevandoskiLS13a fatcat:cl4cxmpoovfgbkmp5npfe4gd6u
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