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Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power [chapter]

Stefanos Kaxiras, Zhigang Hu, Girija Narlikar, Rae McLellan
2001 Lecture Notes in Computer Science  
We find that it is possible with cache-line decay to build larger caches that dissipate less leakage power than smaller caches while yielding equal or better performance.  ...  Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadvertently will lead to an exponential increase in leakage power dissipation.  ...  Conclusions In this paper we propose cache decay, a mechanism to reduce leakage power dissipation in Active ratio 32K S tandard 32K Decay caches.  ... 
doi:10.1007/3-540-44572-2_7 fatcat:edcaw5mi7fcrdarixkv7ssy6oe

Prefetching-aware cache line turnoff for saving leakage energy

Ismail Kadayif, Mahmut Kandemir, Feihui Li
2006 Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06  
These schemes treat prefetched cache lines differently from the lines brought to the cache in a normal way (i.e., through a load operation) in turning off the cache lines.  ...  More importantly, we propose three optimization schemes that turn off cache lines in a prefetchingsensitive manner.  ...  An important requirement to reduce leakage energy using either a state-destroying (cache line turnoff) or a statepreserving leakage control mechanism is the ability to identify unused resources (cache  ... 
doi:10.1145/1118299.1118351 fatcat:mg2uchm6dffwzjwjmwgrb6c3kq

IATAC: a smart predictor to turn-off L2 cache lines

Jaume Abella, Antonio González, Xavier Vera, Michael F. P. O'Boyle
2005 ACM Transactions on Architecture and Code Optimization (TACO)  
This paper introduces IATAC (inter-access time per access count), a new hardware technique to reduce cache leakage for L2 caches.  ...  IATAC dynamically adapts the cache size to the program requirements turning off cache lines whose content is not likely to be reused.  ...  The main idea of this work is reducing the supply voltage by putting cache lines in drowsy mode (a kind of sleep mode) to reduce their leakage without losing their contents.  ... 
doi:10.1145/1061267.1061271 fatcat:mxnydqlpunbfpfbardufsx5bjy

Cache decay

Stefanos Kaxiras, Zhigang Hu, Margaret Martonosi
2001 SIGARCH Computer Architecture News  
While the bulk of the power dissipated is dynamic switching power, leakage power is also beginning to be a concern.  ...  We discuss policies and implementations for reducing cache leakage by invalidating and "turning off" cache lines when they hold data not likely to be reused.  ...  Our thanks to Jim Goodman who turned our attention to adaptive decay techniques and to Alan J. Smith for pointing out LRU decay and multiprogramming.  ... 
doi:10.1145/384285.379268 fatcat:reh2x2cj2nfd3kdytq7ptin6mq

Adaptive VP decay

Juan M. Cebrian, Juan L. Aragon, Jose M Garcia, Stefanos Kaxiras
2007 Proceedings of the 4th international conference on Computing frontiers - CF '07  
access behaviour than caches, in order to reduce their leakage energy efficiently compromising neither VP accuracy nor the speedup provided.  ...  Recent techniques, aimed at reducing the leakage power of array structures such as caches, either switch off (non-state preserving) or reduce the voltage level (statepreserving) of unused array portions  ...  [20] show an adaptive time based mechanism suited for caches to dynamically disable cache lines in order to reduce leakage power dissipation.  ... 
doi:10.1145/1242531.1242550 dblp:conf/cf/CebrianAGK07 fatcat:b3tye5hbfzfunb3ztmhxo3xena

Leakage Energy Reduction in Value Predictors through Static Decay

Juan M. Cebrian, Juan L. Aragon, Jose M. Garcia
2007 2007 IEEE International Parallel and Distributed Processing Symposium  
Our mechanism reduces VP leakage energy efficiently without compromising VP accuracy nor processor performance.  ...  This paper proposes the design of low-leakage Value Predictors by applying static decay techniques in order to disable unused entries from the prediction tables.  ...  Cache Decay [10] selectively turns individual data cache lines off if they have not been used in a long time, reducing leakage power at the cost of loosing the content of the cache line.  ... 
doi:10.1109/ipdps.2007.370537 dblp:conf/ipps/CebrianAG07 fatcat:l5fvkmpyvvfgvpyj544h6pxs7m

Profile-based adaptation for cache decay

Karthik Sankaranarayanan, Kevin Skadron
2004 ACM Transactions on Architecture and Code Optimization (TACO)  
Cache decay" is a set of leakage-reduction mechanisms that put cache lines that have not been accessed for a specific duration into a low-leakage standby mode.  ...  This work explicitly trades off the leakage power saved in putting both the "live" and "dead" lines into standby mode, against its performance and energy costs.  ...  We would like to express our sincere thanks to the editor, the reviewers, and Mircea Stan for their helpful and constructive feedback.  ... 
doi:10.1145/1022969.1022972 fatcat:fdqwfkwi6vh65acblshny6dryi

Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs

Matteo Monchiero, Ramon Canal, Antonio Gonzalez
2009 2009 International Conference on Parallel Processing  
In this case, coherence must be enforced in all situations and specially when a line is turned off to save power.  ...  This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches.  ...  They show that the leakage power of a gated cell can be reduced virtually to zero, at the cost of 8% slower access time and 5% area increase.  ... 
doi:10.1109/icpp.2009.28 dblp:conf/icpp/MonchieroCG09 fatcat:3wllmsscl5bpxdp4xi3nmxmu2i

Applying Decay to Reduce Dynamic Power in Set-Associative Caches [chapter]

Georgios Keramidas, Polychronis Xekalakis, Stefanos Kaxiras
2007 Lecture Notes in Computer Science  
In this paper, we propose a novel approach to reduce dynamic power in set-associative caches that leverages on a leakage-saving proposal, namely Cache Decay.  ...  We thus open the possibility to unify dynamic and leakage management in the same framework. The main intuition is that in a decaying cache, dead lines in a set need not be searched.  ...  Having a decaying cache to reduce leakage, one would have to pay for this dynamic-power penalty regardless of any additional mechanism for dynamic power reduction.  ... 
doi:10.1007/978-3-540-69338-3_4 fatcat:d4pcwmgyajctxbaana3t4vv3du

Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches [chapter]

Georgios Keramidas, Polychronis Xekalakis, Stefanos Kaxiras
2009 Lecture Notes in Computer Science  
In this paper, we propose a novel approach to reduce dynamic power in set-associative caches that leverages on a leakage-saving proposal, namely Cache Decay.  ...  We thus open the possibility to unify dynamic and leakage management in the same framework. The main intuition is that in a decaying cache, dead lines in a set need not be searched.  ...  Having a decaying cache to reduce leakage, one would have to pay for this dynamic-power penalty regardless of any additional mechanism for dynamic power reduction.  ... 
doi:10.1007/978-3-642-00904-4_2 fatcat:5ud3ga2lsvdklpay2jlc226w4q

4T-decay sensors

Stefanos Kaxiras, Polychronis Xekalakis
2004 Proceedings of the 2004 international symposium on Low power electronics and design - ISLPED '04  
Decaying 4T sensors also provide a measurement of the level of leakage at their sensing area, allowing us to adjust leakage-control policies.  ...  We present a novel temperature/leakage sensor, developed for high-speed, low-power, monitoring of processors and complex VLSI chips.  ...  interval that maximizes leakage-power savings for a specific temperature; second, they can help identify parts of the cache that heat up and need leakage-control, as opposed to cool parts of the cache  ... 
doi:10.1145/1013235.1013268 dblp:conf/islped/KaxirasX04 fatcat:c4vf4zlrqremxml3u5tuiykyyy

Implementing branch-predictor decay using quasi-static memory cells

Philo Juang, Kevin Skadron, Margaret Martonosi, Zhigang Hu, Douglas W. Clark, Philip W. Diodato, Stefanos Kaxiras
2004 ACM Transactions on Architecture and Code Optimization (TACO)  
For these reasons, it is natural to consider applying decay techniques-already shown to reduce leakage energy for caches-to branch-prediction structures.  ...  Due to the structural difference between caches and branch predictors, applying decay techniques to branch predictors is not straightforward.  ...  Kevin Skadron's research was supported in part by NSF grants CCR-0105626, an NSF CAREER award (CCR-0133634), and a grant from Intel MRL.  ... 
doi:10.1145/1011528.1011531 fatcat:d4kzsf5lyvbezpmlf7us445oyy

Managing leakage for transient data: decay and quasi-static 4T memory cells

Zhigang Hu, Philo Juang, P. Diodato, S. Kaxiras, K. Skadron, M. Martonosi, D.W. Clark
2002 Proceedings of the International Symposium on Low Power Electronics and Design  
More broadly, this paper suggests a new view of how to support transient data in power-aware processors.  ...  These cells have no connection to Vdd and thus inherently provide decay functionality: values are refreshed upon access but discharge over time without use.  ...  [6] applied decay strategies to branch predictors. These techniques use counters to gauge how long cache lines have been idle.  ... 
doi:10.1109/lpe.2002.146708 fatcat:6lxb4tlkvbdjhpurnxdnonrw6a

Reducing Leakage through Filter Cache

Roberto Giorgi, Paolo Bennati
2008 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools  
The key idea is to reduce the lifetime of the lines that are in high-power state inside a leakage-saving cache.  ...  We discovered that a filter cache, traditionally used for reducing active power, can help reduce also leakage.  ...  Acknowledgments We are particularly grateful to Prof. Sally McKee form Cornell University for providing us with a modified version of HotLeakage retargeted for ARM ISA.  ... 
doi:10.1109/dsd.2008.123 dblp:conf/dsd/GiorgiB08 fatcat:dtjhjbyvo5bjrdl3aawmdp26d4

Exploiting temporal locality in drowsy cache policies

Salvador Petit, Julio Sahuquillo, Jose M. Such, David Kaeli
2005 Proceedings of the 2nd conference on Computing frontiers - CF '05  
Non-state preserving techniques power off selected cache lines while state preserving place selected lines into a low-power state. Drowsy caches are a recently proposed state-preserving technique.  ...  In order to introduce low performance overhead, drowsy caches must be very selective which cache lines are moved to a drowsy state.  ...  Leakage Control for Caches: Vdd and Drowsy Caches A common technique applied to reduce leakage in caches is to reduce the power supplied.  ... 
doi:10.1145/1062261.1062321 dblp:conf/cf/PetitSSK05 fatcat:uuortwjv2zaibknvxcuvbrszim
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