A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2014; you can also visit the original URL.
The file type is application/pdf.
Filters
Cache-Based Scalable Deep Packet Inspection with Predictive Automaton
2010
2010 IEEE Global Telecommunications Conference GLOBECOM 2010
Preserved Fulltext
We define the concept of local prediction which predicts the memory accesses to the DFA and guides the cache to be replaced with proper states so that the cache hit rate is greatly raised. ...
To improve the performance, we propose a generalized caching scheme that strike the boundaries of memory size. ...
We design the caching scheme using a separation of caching policy and caching mechanism. ...
doi:10.1109/glocom.2010.5683142
dblp:conf/globecom/TangJWWL10
fatcat:ehq75mwq3zfkpafryz6vm3ovfe
Cache-Conscious Automata for XML Filtering
2006
IEEE Transactions on Knowledge and Data Engineering
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2011; you can also visit the original URL.
The file type is application/pdf.
Furthermore, we propose a cache-conscious automaton organization technique, called the hot buffer, to improve the locality of automaton state transitions. ...
In this paper, we study the cache performance of automaton-based XML filtering through analytical modeling and system measurement. ...
We say a node of a tag tree resides in the cache if the corresponding state in the automaton resides in the cache. ...
doi:10.1109/tkde.2006.184
fatcat:qbmya4zkw5bfxmtzv4u6kawg4y
A Security Verification Template to Assess Cache Architecture Vulnerabilities
2020
2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
To address this shortcoming, we propose a security verification methodology that formally verifies cache designs against cache side-channel vulnerabilities. ...
Results show that this verification template is a straightforward, automated method in verifying cache invulnerability. ...
It again synchronizes this information with the cache automaton and the cache automaton repeats the same operations as during Stage 1. ...
doi:10.1109/ddecs50862.2020.9095707
dblp:conf/ddecs/GhasempouriRPRH20
fatcat:lu6whtyjnjde3gwtnkvzyau544
Unification of Publish/Subscribe Systems and Stream Databases
[chapter]
2012
Lecture Notes in Computer Science
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
The paper describes the architecture for this unified system, the automaton programming language that it supports, and the run-time system that animates automata. ...
This is followed by a discussion of the cache architecture, the automaton programming language, and the automaton execution model. ...
execution model When an application registers an automaton against the Cache, it provides the source code for the automaton along with data required for the cache to create an RPC channel back to the ...
doi:10.1007/978-3-642-35170-9_15
fatcat:w43kejl4anbmtf577uaw4a45dm
Finite Automata Implementations Considering CPU Cache
2007
Acta Polytechnica
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
We present two main approaches to practical implementation of DFA considering CPU cache. ...
More general finite automaton is the nondeterministic finite automaton (NFA) that cannot be directly used. ...
Suffix automaton and factor automaton (automaton recognizing all suffixes and factors of the given string, respectively) [3, 4] are of such kind. ...
doaj:b36cb015f8d64d9d8af4582b6c610982
fatcat:ynj32tlry5axfbvkdcymlmoicu
Modeling Cache Coherence to Expose Interference
2019
Euromicro Conference on Real-Time Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
To facilitate programming, most multi-core processors feature automated mechanisms maintaining coherence between each core's cache. ...
Consequently, this paper proposes a nascent framework relying on timed automata to model and analyze the interference caused by cache coherence. ...
Cache Controller The automaton used to model a cache controller is rather complex. ...
doi:10.4230/lipics.ecrts.2019.18
dblp:conf/ecrts/SensfelderBP19
fatcat:lb5lvckgvfffxc6zqptnytxskq
Models of concurrent program running in resource constrained environment
2020
PROBLEMS IN PROGRAMMING
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
The paper considers concurrent program modeling using resource constrained automatons. ...
An example of cache memory behavior is presented at figure 4. The figure shows the number of cache misses into instruction cache and 1 st and 2 nd levels of data cache. ...
For these operations the execution time is mainly defined by CPU cache configuration, cache renewal policy and cache misses. ...
doi:10.15407/pp2020.02-03.149
fatcat:utpufnlqgjc6floc3biunxzlrq
ESW4
1999
Computer communication review
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
We discuss a cache management scheme involving the relocation of full caches to the most candidate cells but also percentages of the cache to less likely neighbors. ...
Relocation is performed according to the output of a movement prediction algorithm based on a learning automaton. The simulation of ESW4 shows substantial benefits for the end user. ...
More specifically, we adopt the use of a learning automaton [38] . ...
doi:10.1145/505696.505700
fatcat:6wbp3m5rqzdililgba37wvix2q
Timed Automata for Modelling Caches and Pipelines
2015
Electronic Proceedings in Theoretical Computer Science
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
Other Versions
In this paper, we focus on modelling the timing aspects of binary programs running on architectures featuring caches and pipelines. ...
The objective is to obtain a timed automaton model to compute tight bounds for the worst-case execution time (WCET) of the programs using model-checking techniques. ...
Hence the automaton of Fig. 3 is a good cache model for this program for any number of switches N. ...
doi:10.4204/eptcs.196.4
fatcat:7twymi4derbydgzz74hork6ib4
Glasgow automata illustrated
2012
Proceedings of the 6th ACM International Conference on Distributed Event-Based Systems - DEBS '12
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
The imperative programming style of the Glasgow Automaton Programming Language (GAPL) enables multiple, efficient realisations of the two challenge queries. ...
The challenge is solved using Glasgow automata, concise complex event processing engines executable in the context of a topic-based publish/subscribe cache of event streams and relations. ...
The paper provides a brief tour of the cache and its automaton programming language in §2. ...
doi:10.1145/2335484.2335522
dblp:conf/debs/KoliousisS12
fatcat:giq5u6247bcltllhdzbw75r5ue
Using proxy cache relocation to accelerate Web browsing in wireless/mobile communications
2001
Proceedings of the tenth international conference on World Wide Web - WWW '01
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
A cache management scheme is proposed, which involves the relocation of full caches to the most probable cells but also percentages of the caches to less likely neighbors. ...
Relocation is performed according to a movement prediction algorithm based on a learning automaton. The simulation of the scheme demonstrates substantial benefits for the end user. ...
More specifically, we adopt the use of a learning automaton [36] . ...
doi:10.1145/371920.371927
dblp:conf/www/HadjiefthymiadesM01
fatcat:4ayuzyth6fg7vlfmnzq3k2rh34
An inheritance-based technique for building simulation proofs incrementally
2002
ACM Transactions on Software Engineering and Methodology
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Figure 2 2 Write-through cache automaton.
Figure 3 3 Atomic write-through cache automaton. ...
Figure 3 presents an atomic write-through cache automaton, atomic write through cache, as a specialization of write through cache. ...
doi:10.1145/504087.504090
fatcat:jsn5tpnow5dpjptn5f27m5bfgy
An inheritance-based technique for building simulation proofs incrementally
2000
Proceedings of the 22nd international conference on Software engineering - ICSE '00
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Figure 2 2 Write-through cache automaton.
Figure 3 3 Atomic write-through cache automaton. ...
Figure 3 presents an atomic write-through cache automaton, atomic write through cache, as a specialization of write through cache. ...
doi:10.1145/337180.337358
dblp:conf/icse/KeidarKLS00
fatcat:hxuqjruk2zaxbnjd4e2hzue43e
Combining Abstract Interpretation with Model Checking for Timing Analysis of Multicore Software
2010
2010 31st IEEE Real-Time Systems Symposium
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
Based on the cache analysis, we construct a Timed Automaton (TA) to model when the programs access the memory bus. Then we model the shared bus also using timed automata. ...
We use Abstract Interpretation (AI) to analyze the local cache behavior of a program running on a dedicated core. ...
Once the service is completed, a signal is sent back to the program automaton, and then the program automaton can progress. accessBus[0]? ...
doi:10.1109/rtss.2010.30
dblp:conf/rtss/LvYGY10
fatcat:xv72vs7di5epjnqsxi2c4ld6am
Towards WCET Analysis of Multicore Architectures Using UPPAAL
2010
Worst-Case Execution Time Analysis
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
This means that threads will have to share resources (e.g. some level of cache) and communicate and synchronize with each other. There already exist software libraries (e.g. ...
On one extreme, all the cache handling could be done by the C-functions, while the automaton only is used to perform the cache access delay. ...
This automaton represents the timing model of the core (the pipeline etc.) and is the automaton with which the program-automaton synchronizes to execute instructions. ...
doi:10.4230/oasics.wcet.2010.101
dblp:conf/wcet/GustavssonELP10
fatcat:m2z5aiqvjbhkjkx3xvvok4autu
« Previous
Showing results 1 — 15 out of 4,031 results