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Continuous-time hybrid computation with programmable nonlinearities

Ning Guo, Yipeng Huang, Tao Mai, Sharvil Patil, Chi Cao, Mingoo Seok, Simha Sethumadhavan, Yannis Tsividis
2015 ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)  
Arbitrary nonlinear functions used in such equations are implemented by a programmable clockless continuous-time 8b hybrid architecture (ADC+SRAM+DAC) with activitydependent power dissipation.  ...  ACKNOWLEDGMENT We thank Chien-Tang Hu, Doyun Kim, Jianxun Zhu, Teng Yang, Yang Xu, Yu Chen and Zhe Cao for valuable discussions.  ...  PROGRAMMABLE CT NONLINEAR FUNCTION GENERATOR A key feature of our hybrid computing unit is the programmable nonlinear analog function generator. The architecture is shown in Fig. 3 .  ... 
doi:10.1109/esscirc.2015.7313881 dblp:conf/esscirc/GuoHMPCSST15 fatcat:t56lqzlcbngehetqaqkcz35svi

Failover, load sharing and server architecture in SIP telephony

Kundan Singh, Henning Schulzrinne
2007 Computer Communications  
Additionally, we present an overview of the failover mechanism we implemented in our test-bed using the open source MySQL database.  ...  We apply some of the existing web server redundancy techniques for high service availability and scalability to the relatively new IP telephony context.  ...  Acknowledgment Huitao Sheng helped with the initial performance measurement. Jonathan Lennox is the primary architect of our SIP server, sipd, and helped with SIPstone tools.  ... 
doi:10.1016/j.comcom.2006.08.037 fatcat:dsia3mguuvdz7jvu5l2bxmnzui

Distributed and Parallel Path Query Processing for Semantic Sensor Networks

Sung-Jae Jung, Dong-Min Seo, Seungwoo Lee, Hwan-Min Kim, Hanmin Jung
2014 International Journal of Distributed Sensor Networks  
Compared with the conventional BFS algorithm, the proposed algorithm (bidirectional BFS combined with class path lookup approach) achieves performance improvement by 3 orders of magnitude.  ...  Large amount of sensor data are annotated with spatial, temporal, and thematic semantic metadata.  ...  This work utilized scientific and technical contents constructed through "Establishment of the Sharing System for Electronic Information with Core Science and Technology" project (K-13-L02-C01-S02).  ... 
doi:10.1155/2014/438626 fatcat:gfup5vpgevhivnssssfaakj4zy

Solving stochastic resource-constrained project scheduling problems by closed-loop approximate dynamic programming

Haitao Li, Norman K. Womer
2015 European Journal of Operational Research  
It performs particularly well for instances with non-symmetric probability distribution of task durations.  ...  Computational results on the benchmark instances show that our hybrid ADP algorithm is able to obtain competitive solutions with the state-of-the-art algorithms in reasonable computational time.  ...  Salim Rostami for kindly providing their PPGA code for our computational study. We also thank three anonymous referees for their  ... 
doi:10.1016/j.ejor.2015.04.015 fatcat:lwyoy2pzsfhbplhu4aczvrpzka

Creating advanced functions on network processors: experience and perspectives

R. Haas, L. Kencl, A. Kind, B. Metzler, R. Pletka, M. Waldvogel, L. Frelechoux, P. Drox, C. Jeffries
2003 IEEE Network  
Then, for each case study, we present results from prototypes as well as general considerations that also apply to a wider range of system architectures.  ...  In this paper, we present five case studies of advanced networking functions and how a network processor (NP) can provide high-performance and flexible support for each of them.  ...  The CP keeps state for each flow it sees and routes flows in progress to the result of the old hash function and new flows to the result of the new hash function.  ... 
doi:10.1109/mnet.2003.1220696 fatcat:goib5acsjjgpfdwoiwgc2atmzm

A Theoretical Framework for Design Space Exploration of Manycore Processors

Hun Jung, Miao Ju, Hao Che
2011 2011 IEEE 19th Annual International Symposium on Modelling, Analysis, and Simulation of Computer and Telecommunication Systems  
This design approach makes the simulation tool generic and adaptable to a wide range of CP architectures with the addition of a set of user provided plug-ins, capturing CP architecture specific features  ...  The rest are generic or common features pertaining to all the CP architectures. This indicates that our simulation tool is indeed generic and easily adaptable to a specific CP architecture.  ...  ∑ and G is the so-called normalization constant or generation function of the system and it is given by: The 's are the relative state probabilities of the state at the node i , which are defined as follows  ... 
doi:10.1109/mascots.2011.21 dblp:conf/mascots/JungJC11 fatcat:uwy73c4ge5c2ln6rrptlhjwlwq

Concury: A Fast and Light-weighted Software Load Balancer [article]

Shouqian Shi, Chen Qian, Ye Yu, Xin Li, Ying Zhang, Xiaozhou Li
2019 arXiv   pre-print
A load balancer (LB) is a vital network function for cloud services to balance the load amongst resources.  ...  The key innovation of Concury is an algorithmic approach to store and look up large network states with frequent connection arrivals, which is succinct in memory cost, consistent under network changes,  ...  We conduct two well-known statistical tests, the chi-squared test and Kolmogorov-Smirnov test, to compare Concury, MD5, and SHA256 with the uniform distribution.  ... 
arXiv:1908.01889v1 fatcat:vf6nozsymvggrebbuhybvmcdlm

IBM PowerNP network processor: Hardware, software, and applications

J. R. Allen, B. M. Bass, C. Basso, R. H. Boivie, J. L. Calvignac, G. T. Davis, L. Frelechoux, M. Heddes, A. Herkersdorf, A. Kind, J. F. Logan, M. Peyravian (+4 others)
2003 IBM Journal of Research and Development  
The key advantage of network processors is that hardware-level performance is complemented by flexible software architecture.  ...  Its hardware and software design characteristics and its comprehensive base operating software make it well suited for a wide range of networking applications.  ...  NPTest provides developers with the environment needed for the initial testing of picocode and for test-case regression.  ... 
doi:10.1147/rd.472.0177 fatcat:nn4smaizkjdxbp7tz4hbrjzvhq

Towards Scalable and Efficient Architecture for Modeling Trust in IoT Environments

Mustafa Ghaleb, Farag Azzedin
2021 Sensors  
Before hosting trust models, suitable architecture for Fog computing is needed to provide scalability, fast data access, simple and efficient intra-communication, load balancing, decentralization, and  ...  In this article, we propose scalable and efficient Chord-based horizontal architecture. We also show how trust modeling can be mapped to our proposed architecture.  ...  We have 64 nodes each generating 1 lookup every 1 min, and as a total, we have around 1 lookup per second. Nodes joining and leaving are modeled randomly with an average of 400 s.  ... 
doi:10.3390/s21092986 pmid:33923182 fatcat:hhu43y4d7ncjzcp57hlvjsg3sy

An object oriented architecture

William J. Dally, James T. Kajiya
1985 SIGARCH Computer Architecture News  
We propose a new machine architecture for high performance execution of late binding object oriented languages.  ...  The two principal mechanisms for attaining this goal are a fast context allocation/access scheme and an instruction translation lookaside buffer.  ...  Figure 9 . 9 Example of compi~d code. §5 Experimental ResultsThis section presents the results of experiments run to test the utility of hardware support for method lookup.  ... 
doi:10.1145/327070.327151 fatcat:7umunkal7fgqnnqc253jqovcva


Zaafar Ahmed, Muhammad Hamad Alizai, Affan A. Syed
2018 Computer communication review  
InKeV addresses these concerns: The use of eBPF allows it to dynamically insert programmable network functions into a running kernel, requiring neither to package a customkernel nor to hope for acceptance  ...  Its novel stitching feature allows to flexibly configure complete virtual networks by creating a graph of network functions inside the kernel.  ...  Hence, exploring this general feasibility, and a complete CP architecture for NV delineates our primary future work.  ... 
doi:10.1145/3243157.3243161 fatcat:eulh4ikb5jds3h6sekfb32vh2a


Darius Mercadier, Pierre-Évariste Dagand, Lionel Lacassagne, Gilles Muller
2018 Proceedings of the 2018 4th Workshop on Programming Models for SIMD/Vector Processing - WPMVP'18  
invariants to perform various optimizations before handing the generated code to an (optimizing) C compiler.  ...  Usuba is both a domain-specific language -providing syntactic support for the implementation of cryptographic algorithms -as well as a domain-specific compiler -taking advantage of welldefined semantics  ...  We are thankful to Intel France and Francois Hannebicq for allowing us to run our experiments on one of their Xeon Skylake Platinium 8168.  ... 
doi:10.1145/3178433.3178437 dblp:conf/ppopp/MercadierDLM18 fatcat:rttklxypobgnzjoum4w2udcpee

Scalable IP lookup for internet routers

D.E. Taylor, J.S. Turner, J.W. Lockwood, T.S. Sproull, D.B. Parlour
2003 IEEE Journal on Selected Areas in Communications  
IP address lookup is a central processing function of Internet routers.  ...  This architecture allows performance to scale up directly with available memory bandwidth.  ...  We also would like to thank Tucker Evans and Ed Spitznagel for their contributions to the FIPL Memory Manager software, as well as John DeHart for his invaluable assistance with system verification and  ... 
doi:10.1109/jsac.2003.810507 fatcat:lpvm6mb7azbcfgkolix2te4eoa

A Modified Run Length Coding Technique For Test Data Compression Based On Multi-Level Selective Huffman Coding

C. Kalamani, K. Paramasivam
2017 Zenodo  
Test data compression is an efficient method for reducing the test application cost.  ...  in scan test applications where redundant length of runs is encountered then the preceding run symbol is replaced with tiny codeword.  ...  The inefficient functionality and increasing the integration size of VLSI chips make testing for these chips more troublesome.  ... 
doi:10.5281/zenodo.1130688 fatcat:bmtx3vmvi5dsxnwa3stwgiz4ba

A Fast Performance Analysis Tool for Multicore, Multithreaded Communication Processors

Hun Jung, Miao Ju, Hao Che, Zhijun Wang
2008 2008 11th IEEE High Assurance Systems Engineering Symposium  
To allow fast communication processor (CP) performance testing of task-to-CP-topology mapping, we propose a fast CP simulation tool * with a few novel ideas that make it generic, fast, and accurate.  ...  Moreover, each simulation run takes only a few seconds to finish on a Pentium III PC, which strongly demonstrates the power of this tool for fast CP performance testing. 2008 11th IEEE High Assurance Systems  ...  This design approach makes the simulation tool generic and adaptable to a wide range of CP architectures with the addition of a set of user provided plug-ins, capturing CP architecture specific features  ... 
doi:10.1109/hase.2008.18 dblp:conf/hase/JungJCW08 fatcat:c2a4xgmo3rfllibabh5j3l5a2m
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