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CMP Design Space Exploration Subject to Physical Constraints

Y. Liy, B. Leez, D. Brooksz, Z. Huyy, K. Skadron
The Twelfth International Symposium on High-Performance Computer Architecture, 2006.  
This paper explores the multi-dimensional design space for chip multiprocessors, exploring the inter-related variables of core count, pipeline depth, superscalar width, L2 cache size, and operating voltage  ...  Thermal constraints dominate other physical constraints such as pin-bandwidth and power delivery, demonstrating the importance of considering thermal constraints while optimizing these other parameters  ...  We would also like to thank Dee A. B. Weikle and the anonymous reviewers for their helpful feedback.  ... 
doi:10.1109/hpca.2006.1598109 dblp:conf/hpca/LiLBHS06 fatcat:ueg4hpsq2ndjbm2q7n4hznfy3y

Physical-aware system-level design for tiled hierarchical chip multiprocessors

Jordi Cortadella, Javier de San Pedro, Nikita Nikitin, Jordi Petit
2013 Proceedings of the 2013 ACM international symposium on International symposium on physical design - ISPD '13  
At the early stages of the design of a CMP, physical parameters are often ignored and postponed for later design stages.  ...  Traditional algorithms for floorplanning and wire planning are customized to include physical constraints specific for tiled hierarchical architectures.  ...  Figure 10 : 10 Example of physical planning search space for a single CMP configuration. Figure 11 : 11 Two design points from the exploration space inFig. 10.  ... 
doi:10.1145/2451916.2451920 dblp:conf/ispd/CortadellaPNP13 fatcat:ufzyr2nvlzg7zd4og7af4oe46u

Convex Optimization of Real Time SoC [article]

L. Yavits, A. Morad, R. Ginosar, U. Weiser
2017 arXiv   pre-print
Convex optimization is shown to be very efficient in a high-level early stage design exploration, guiding computer architects as to the choice of area, voltage, and frequency of the individual components  ...  Convex optimization methods are employed to optimize a real-time (RT) system-on-chip (SoC) under a variety of physical resource-driven constraints, demonstrated on an industry MPEG2 encoder SoC.  ...  While convex optimization relies on analytical modeling and hence cannot replace the full design space exploration, it can be very efficient for a high-level early stage of such exploration, guiding computer  ... 
arXiv:1601.07815v2 fatcat:yxk2n4p23nffhj3woqxxkb2w4q

Multi-product floorplan and uncore design framework for chip multiprocessors

Marco Escalante, Andrew B. Kahng, Michael Kishinevsky, Umit Ogras, Kambiz Samadi
2015 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)  
While it is crucial to optimize the floorplan and uncore of each product class to achieve the best power-performance tradeoff, independent optimization may greatly increase the design effort, and undermine  ...  Chip multiprocessors (CMPs) for server and high-performance computing markets are offered in multiple classes to satisfy various power, performance and cost requirements.  ...  RELATED WORK Physically-aware NoC link allocation for CMPs is addressed in [7] , while physical planning of large CMPs for architectural exploration is discussed in [8] .  ... 
doi:10.1109/slip.2015.7171713 dblp:conf/slip/EscalanteKKOS15 fatcat:aitf7e66b5cavi5zzksw5m3xoa

Architectural Exploration of Large-Scale Hierarchical Chip Multiprocessors

Nikita Nikitin, Javier de San Pedro, Jordi Cortadella
2013 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Index Terms-Analytical modeling, chip multiprocessing, design space exploration, metaheuristics, numerical methods. 0278-0070 c 2013 IEEE  ...  By using the analytical model as a performance and power estimator, an efficient metaheuristic-based search is proposed for the exploration of large design spaces.  ...  Acknowledgments The authors would like to thank J. Carmona, F. Guim, M. Kishinevsky, and U. Ogras for insightful comments and helpful discussions.  ... 
doi:10.1109/tcad.2013.2272539 fatcat:gvj6nwhgjje7fpaarfimg37mf4

A tangible user interface for assessing cognitive mapping ability

Ehud Sharlin, Benjamin Watson, Steve Sutphen, Lili Liu, Robert Lederer, John Frazer
2009 International Journal of Human-Computer Studies  
We describe the design of the CMP, and find that it is sensitive to factors known to affect cognitive mapping performance in extensive experimental testing. r  ...  The CMP uses a tangible user interface that affords spatial manipulation.  ...  ., 2004) , or explored their social design implications (Hornecker and Buur, 2006) .  ... 
doi:10.1016/j.ijhcs.2008.09.014 fatcat:bfs7omfyfret7bygvcfx7wvhxi

Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random $L_{\rm eff}$ Variation

Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong
2007 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
We first present a quantitative study on the impact of CMP to interconnect parasitics.  ...  We then introduce a simple extension to handle CMP effects in the buffer insertion and wire sizing problem by simultaneously considering fill insertion (SBWF).  ...  Fill Patterns Exploration We explore a wide range of design-rule-check (DRC) correct fill patterns.  ... 
doi:10.1109/tcad.2006.884869 fatcat:yknw47ynyvhvhhqfzixmkaxj6m

Architectural implications of brick and mortar silicon manufacturing

Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, Todd Austin
2007 Proceedings of the 34th annual international symposium on Computer architecture - ISCA '07  
We discuss a sample chip design, a 16-way CMP, and analyze the costs and benefits of designing chips with brick and mortar.  ...  Finally, we measure the effect that architectural design decisions have on the behavior of the proposed physical brick assembly technique, fluidic self-assembly.  ...  We explored how to use brick and mortar to assemble made-to-order CMPs and found that such chips perform comparable to fully custom ASIC versions.  ... 
doi:10.1145/1250662.1250693 dblp:conf/isca/KimMOA07 fatcat:e5zb7ge7azdcnie2l47dyfpkwy

Architectural implications of brick and mortar silicon manufacturing

Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, Todd Austin
2007 SIGARCH Computer Architecture News  
We discuss a sample chip design, a 16-way CMP, and analyze the costs and benefits of designing chips with brick and mortar.  ...  Finally, we measure the effect that architectural design decisions have on the behavior of the proposed physical brick assembly technique, fluidic self-assembly.  ...  We explored how to use brick and mortar to assemble made-to-order CMPs and found that such chips perform comparable to fully custom ASIC versions.  ... 
doi:10.1145/1273440.1250693 fatcat:4khr4zb6uzgqnhxfsd6vcec6ju

A design space exploration of transmission-line links for on-chip interconnect

Aaron Carpenter, Jianyun Hu, Michael Huang, Hui Wu, Peng Liu
2011 IEEE/ACM International Symposium on Low Power Electronics and Design  
This paper makes a first-step effort in exploring part of the design space.  ...  While transmission lines have been used in a wide variety of purposes, there lack comprehensive studies to guide architects to navigate the circuit and physical design space to make proper architecture-level  ...  In this paper, we take a first-step effort exploring the design space of TL circuitry.  ... 
doi:10.1109/islped.2011.5993647 fatcat:bhswpy27kzcwnjse77g7nj5m2i

Area-efficiency in CMP core design

Omid Azizi, Aqeel Mahesri, Sanjay J. Patel, Mark Horowitz
2009 SIGARCH Computer Architecture News  
In this paper, we examine the area-performance design space of a processing core for a chip multiprocessor (CMP), considering both the architectural design space and the tradeoffs of the physical design  ...  In our approach, we use statistical and convex fitting methods to capture a large micro-architectural design space.  ...  to interesting design space exploration studies.  ... 
doi:10.1145/1577129.1577138 fatcat:bpp3llavirhf3oe5the7r6qcji

Beyond Amdahl's Law: An Objective Function That Links Multiprocessor Performance Gains to Delay and Energy

Andrew S. Cassidy, Andreas G. Andreou
2012 IEEE transactions on computers  
Following the derivation, we demonstrate its utility by applying it to the problem of Chip Multi-Processor (CMP) architecture exploration.  ...  We find the parameters that minimize the total system cost, defined by the objective function under the area constraint of a single die.  ...  Amdahl's Law as a cost function formulation that includes the energy-delay product was inspired by the "Bandwidth-Cost Integral," an idea that was conceived by the members of the working group "Obstacles to  ... 
doi:10.1109/tc.2011.169 fatcat:qlgfx257hjandkit22v3wmnzyq

CMP Fill Synthesis [chapter]

Andrew Kahng, Kambiz Samadi
2008 Handbook of Algorithms for Physical Design Automation  
In addition, we discuss the concept of design-driven fill synthesis that seeks to optimize CMP fill with respect to objectives beyond mere density uniformity.  ...  Index Terms-Chemical-mechanical polishing (CMP), CMP fill, design-driven fill, topography.  ...  Therefore, to restrict the space of exploration, He et al.  ... 
doi:10.1201/9781420013481.ch36 fatcat:5u2ufr4ulrfybau7lhky3i7u6q

Core architecture optimization for heterogeneous chip multiprocessors

Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi
2006 Proceedings of the 15th international conference on Parallel architectures and compilation techniques - PACT '06  
However, none of those studies examined how to design such a processor; instead, they started with an assumed combination of pre-existing cores.  ...  This work assumes the flexibility to design a multi-core architecture from the ground up and seeks to address the following question: what should be the characteristics of the cores for a heterogeneous  ...  Acknowledgments The authors would like to thank Saisanthosh Balakrishnan, Jeff Collard, Soraya Ghiasi, Tomer Morad, and Partha Ranganathan for their valuable comments at various stages of this research  ... 
doi:10.1145/1152154.1152162 dblp:conf/IEEEpact/KumarTJ06 fatcat:nxca5scsdngpnkumwg74a4si6q

Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing

Nikita Nikitin, Satrajit Chatterjee, Jordi Cortadella, Mike Kishinevsky, Umit Ogras
2010 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip  
The solution of the problem meets the physical and performance constraints defined by the designer. The method guarantees that the generated solution is deadlock free.  ...  The architecture definition, design, and validation of the interconnect networks is a key step in the design of modern on-chip systems.  ...  The proposed IP model enables the designer to perform network topology exploration and tuning, subject to a large set of user-defined constraints.  ... 
doi:10.1109/nocs.2010.22 dblp:conf/nocs/NikitinCCKO10 fatcat:stfrzl2uxfg4df3m5itoebje4i
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