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CHIPPER: A low-complexity bufferless deflection router

Chris Fallin, Chris Craik, Onur Mutlu
2011 2011 IEEE 17th International Symposium on High Performance Computer Architecture  
However, current bufferless designs usually add complexity to control logic. Deflection routing introduces a sequential dependence in port allocation, yielding a slow critical path.  ...  In particular, recent work proposes bufferless deflection routing to eliminate router buffers.  ...  Conclusions We presented CHIPPER, a router design for bufferless deflection networks that drastically reduces network power and hardware cost with minimal performance degradation for systems with low-to-medium  ... 
doi:10.1109/hpca.2011.5749724 dblp:conf/hpca/FallinCM11 fatcat:4birjeoienflhn7n4lz7bkqqqi

CHIPPER: A Low-complexity Bufferless Deflection Router

Chris Fallin, Chris Craik, Onur Mutlu
2018
In particular, recent work proposes bufferless deflection routing to eliminate router buffers.  ...  To counter this, we propose CHIPPER (Cheap-Interconnect Partially Permuting Router), a simplified router microarchitecture that eliminates in-routerbuffers and the crossbar.  ...  Conclusions We presented CHIPPER, a router design for bufferless deflection networks that drastically reduces network power and hardware cost with minimal performance degradation for systems with low-to-medium  ... 
doi:10.1184/r1/6468497 fatcat:wvh6zeood5cc7irkig2eawsyou

Bus Based Synchronization Method for CHIPPER Based NoC

D. Muralidharan, R. Muthaiah
2016 Scientific Programming  
Bufferless NoC reduces the area complexity and power consumption by eliminating buffers in the traditional routers.  ...  Live lock freeness is provided in CHIPPER through golden epoch and golden packet. All routers follow some synchronization method to identify a golden packet.  ...  Due to these advantages CHIPPER is considered as a low overhead, live lock free, bufferless technique. Throughput enhancement of CHIPPER is analyzed in MD [19] and MINBD [17] .  ... 
doi:10.1155/2016/1907521 fatcat:zu6orilx4vcgjb77ewmit27xey

Bufferless and Minimally-Buffered Deflection Routing [chapter]

Chris Fallin, Greg Nazario, Xiangyao Yu, Kevin Chang, Rachata Ausavarungnirun, Onur Mutlu
2013 Routing Algorithms in Networks-on-Chip  
This minimally-buffered deflection (MinBD) router improves performance relative to bufferless deflection routing without incurring the cost of a large buffer, because it can make more efficient use of  ...  The result is a router design which is more energy-efficient than prior buffered, bufferless, and hybrid router designs. 1 1 One recent estimate indicates that static power (of buffers and links) could  ...  Acknowledgments We thank the anonymous reviewers of our conference papers CHIPPER [17] and MinBD [20] for their feedback.  ... 
doi:10.1007/978-1-4614-8274-1_10 fatcat:edzwfbsgo5fi7idw45nnswthya

MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect

Chris Fallin, Greg Nazario, Xiangyao Yu, Kevin Chang, Rachata Ausavarungnirun, Onur Mutlu
2012 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip  
In this work, we propose a new NoC router design called the minimally-buffered deflection (MinBD) router.  ...  We evaluate MinBD against input-buffered routers of various sizes that implement buffer bypassing, a bufferless router, and a hybrid design, and show that MinBD is more energy-efficient than all prior  ...  BLESS [28] , another bufferless deflection network, uses a more complex deflection routing algorithm.  ... 
doi:10.1109/nocs.2012.8 dblp:conf/nocs/FallinNYCAM12 fatcat:lj2x4dei7rah7kiieguohuwece

A 1-Cycle 1.25GHz Bufferless Router for 3D Network-on-Chip

Chaochao FENG, Zhonghai LU, Axel JANTSCH, Minxuan ZHANG
2012 IEICE transactions on information and systems  
In this paper, we propose a 1-cycle high-performance 3D bufferless router with a 3-stage permutation network.  ...  Compared with the other two 3D bufferless routers, the proposed router occupies less area and consumes less power consumption.  ...  A low-complexity bufferless router (called CHIPPER) has been proposed in [4] for 2D mesh NoC. A partial permutation network is used to replace the switch allocator and crossbar in the router.  ... 
doi:10.1587/transinf.e95.d.1519 fatcat:2xtgzakrmvffxhheb5vd7mjnvm

Energy-Efficient Deflection-based On-chip Networks: Topology, Routing, Flow Control [article]

Rachata Ausavarungnirun, Onur Mutlu
2021 arXiv   pre-print
To mitigate this high energy cost, many works propose bufferless router designs that utilize deflection routing to resolve port contention.  ...  While this approach is able to maintain high performance relative to its buffered counterparts at low network traffic, the bufferless router design suffers performance degradation under high network load  ...  We also compare our mechanism against CHIPPER [4] , a low-complexity bufferless mesh network. We use 128-bit links for both designs.  ... 
arXiv:2112.02516v2 fatcat:vhrsn7lknncgnaxf7ycw6ylzam

Implementation of Input Block of Minimally Buffered Deflection NoC Router

Priti M. Shahane, Narayan Pisharoty
2016 International Journal of Engineering and Technology  
The MinBD (minimally buffered deflection) router is a new router design that uses a small buffer for bufferless deflection routing.  ...  Various bufferless routing algorithms have been proposed to overcome the disadvantages of a buffered router [4, 5, 6, 7, 8]. CHIPPER and BLESS are the best examples of bufferless routers [5, 7].  ...  So router should buffer a data packet if required. Thus data packets that would have been deflected in a bufferless deflection router are removed from the network temporarily into side buffer.  ... 
doi:10.21817/ijet/2016/v8i4/160804415 fatcat:egrox5a5jzgv3bkk6hwnmopiiq

Evaluation of Bufferless Network-On-Chip with Parallel Port Allocator

Cecil C Nachiar, Sumathi S
2021 International Research Journal on Advanced Science Hub  
To overcome this, we have designed a bufferless architecture with local bypass ring within nodes to reduce deflection and packet loss.  ...  Our paper proposes efficient bufferless design with deflection containment technique to eliminate buffers and latency.  ...  CHIPPER [8], low complexity buffer has simplified router micro architecture by removing in router buffers and crossbars. It is based on Golden packet and retransmit once algorithms.  ... 
doi:10.47392/irjash.2021.074 fatcat:47ezfvhct5gfzig7kd2m7ainci

A survey on energy-efficient methodologies and architectures of network-on-chip

Assad Abbas, Mazhar Ali, Ahmad Fayyaz, Ankan Ghosh, Anshul Kalra, Samee U. Khan, Muhammad Usman Shahid Khan, Thiago De Menezes, Sayantica Pattanayak, Alarka Sanyal, Saeeda Usman
2014 Computers & electrical engineering  
We present a survey that provides a broad picture of the state-of-the-art energy-efficient NoC architectures and techniques, such as the routing algorithms, buffered and bufferless router architectures  ...  Integration of large number of electronic components on a single chip has resulted in complete and complex systems on a single chip.  ...  Flit deflection 8 Â 8 mesh U - U [8] Bufferless Deflection Custom 64 Â 64 BLOCON topology U U U - [29] Hybrid Threshold based switching 3 Â 3 mesh - - U U [28] Hybrid Buffer optimization  ... 
doi:10.1016/j.compeleceng.2014.07.012 fatcat:ltk46h5gd5azxhsfeuyyat3pte

QBLESS: A case for QoS-aware bufferless NoCs

Zhicheng Yao, Xiufeng Sui, Tianni Xu, Jiuyue Ma, Juan Fang, Sally A. McKee, Binzhang Fu, Yungang Bao
2014 2014 IEEE 22nd International Symposium of Quality of Service (IWQoS)  
We propose QBLESS, a QoSaware bufferless NoC scheme for datacenters.  ...  QBLESS consists of two components: a routing mechanism (QBLESS-R) that can substantially reduce flit deflection for high-priority applications, and a congestion-control mechanism (QBLESS-CC) that guarantees  ...  [19] propose the CHIPPER router architecture to reduce the complexity of BLESS control logic.  ... 
doi:10.1109/iwqos.2014.6914305 dblp:conf/iwqos/YaoSXMFMFB14 fatcat:ljnl53ov2ffz5p564kvubbqs44

Ephedrine QoS: An Antidote to Slow, Congested, Bufferless NoCs

Juan Fang, Zhicheng Yao, Xiufeng Sui, Yungang Bao
2014 The Scientific World Journal  
We propose QBLESS, a QoS-aware bufferless NoC scheme for datacenters.  ...  QBLESS consists of two components: a routing mechanism (QBLESS-R) that can substantially reduce flit deflection for high-priority applications and a congestion-control mechanism (QBLESS-CC) that guarantees  ...  [18] propose the CHIPPER router architecture to reduce the complexity of BLESS control logic.  ... 
doi:10.1155/2014/691865 pmid:25250386 pmcid:PMC4163332 fatcat:t3oceiffofhyngoaolho5c3iwq

Design and Implementation of Single Node NoC Router using Small Side Buffer in Input Block and iSLIP Scheduler

Priti Shahane
2020 International Journal of Advanced Trends in Computer Science and Engineering  
Bufferless deflection routing will be the solution for improvement in power efficiency, but latency might increase due to unnecessary hopping of data packets.  ...  NoC provides a solution for communication infrastructure for SoC. The router is a foremost element of NoC which significantly impacts the performance of NoC.  ...  The best examples of bufferless routers are the CHIPPER and BLESS [13] - [15] .  ... 
doi:10.30534/ijatcse/2020/222942020 fatcat:ujfpu26dlfbkdemmfztpbscj3a

Deflection routing in 3D Network-on-Chip with TSV serialization

Jinho Lee, Dongwoo Lee, Sunwook Kim, Kiyoung Choi
2013 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)  
Fallin et. al, "CHIPPER: A low-complexity bufferless deflection router," in Proc. power consumption on high load -Additional information on each flit • Deflection routing is naturally adaptive in a very  ...  bufferless deflection routing is suggested on 3D NoC with TSV serialization. • Some problems are solved.  ... 
doi:10.1109/aspdac.2013.6509554 dblp:conf/aspdac/LeeLKC13 fatcat:qildii44cvfeflb33bv3h5adta

Smart Port Allocation for Adaptive NoC Routers

Reenu James, John Jose, Jobin K. Antony
2015 2015 28th International Conference on VLSI Design  
Considering the cost effective performance and scalability, minimally buffered deflection routers are emerging as a popular design choice for NoC based multicore systems.  ...  when compared to the state-of-the-art minimally buffered deflection routers.  ...  NoC with bufferless deflection routers is emerging as a better design choice for low-injection rate applications.  ... 
doi:10.1109/vlsid.2015.86 dblp:conf/vlsid/JamesJA15 fatcat:4hib3gtgkveqhexvgi5tc5pw5m
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