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Coherence and Replacement Protocol of DICE—A Bus-Based COMA Multiprocessor

Sangyeun Cho, Jinseok Kong, Gyungho Lee
1999 Journal of Parallel and Distributed Computing  
We present performance results that show a drastic reduction in global bus traffic compared to a traditional shared-bus multiprocessor architecture. 1999 Academic Press, Inc.  ...  DICE tries to optimize COMA for a shared-bus medium, in particular to reduce the detrimental effects of cache coherence and the"last memory block" problem on replacement.  ...  Sangyeun Cho was supported in part by a fellowship from the Korea Foundation for Advanced Studies.  ... 
doi:10.1006/jpdc.1998.1524 fatcat:fdu7qc55k5f2jazhvs5sbazdwi

On timing constraints of snooping in a bus-based COMA multiprocessor

Sangyeun Choa, Jinseok Kong, Gyungho Lee
1998 Microprocessors and microsystems  
Cache only memory architecture has the potential to decrease global bus traffic in shared-bus multiprocessors, thereby reducing the speed gap between modem microprocessors and global backplane bus systems  ...  In this paper, we propose a scheme to relax the timing constraints of snooping in a bus-based COMA multiprocessor, which allows an efficient design of a global bus protocol, and a cost-effective implementation  ...  A version of this paper appeared in the Proc. of lASTED International Conference on Parallel and Distributed Computing and Systems, Chicago, IL, October 1996.  ... 
doi:10.1016/s0141-9331(97)00055-0 fatcat:s3o74fusyfa57o7vx6mlolxm44

Global bus design of a bus-based COMA multiprocessor DICE

G. Lee, B. Quattlebaum, S. Cho, L. Kinney
Proceedings International Conference on Computer Design. VLSI in Computers and Processors  
DICE is a shared-bus multiprocessor based on a distributed shared-memory architecture, known as Cache-Only Memory Architecture (COMA).  ...  In this paper, we present a global bus design for a bus-based COMA multiprocessor using the IEEE Fu-turebus+ standard backplane bus and the Texas Instruments chip-set.  ...  The Figure 1 : A bus-based COMA multiprocessor main contribution of this paper is in demonstrating the feasibility of an efficient implementation of a bus-based COMA multiprocessor.  ... 
doi:10.1109/iccd.1996.563562 dblp:conf/iccd/LeeQCK96 fatcat:e536jclz4faqriiawhwgxxyz34

Design of a bus-based shared-memory multiprocessor DICE

Gyungho Lee, Bland W Quattlebaum, Sangyeun Cho, Larry L Kinney
1999 Microprocessors and microsystems  
DICE is a shared-bus multiprocessor based on a distributed shared-memory architecture, known as cache-only memory architecture (COMA).  ...  DICE tries to optimize COMA for a shared-bus medium, in particular to reduce detrimental effects of the cache coherence and the 'last memory block' problem on replacement.  ...  Manu Agarwal, Sujat Jamil and Jinseok Kong contributed to the project on which this work is based. An earlier version of the paper was presented in Ref. [26] .  ... 
doi:10.1016/s0141-9331(98)00097-0 fatcat:gmluftwjg5g3ximidir4rq3b7y

Analytic model of a Cache Only Memory Architecture [chapter]

Carlos Carreras, Carlos A. López, Manuel Hermenegildo
1994 Lecture Notes in Computer Science  
This paper presents an analytic model of a specific shared memory multiprocessor, the bus-based Data Difussion Machine (DDM).  ...  COMA constitute a new approach to design large-scale multiprocessors. The bus-based DDM is a COMA with a coherence protocol supported by a scalable hierarchy of directories and buses.  ...  Small errors in traffic rates in the M-bus cause significant errors in M-bus waiting times and, therefore, in traffic rates reaching the level-1 DDM bus.  ... 
doi:10.1007/3-540-58184-7_113 fatcat:txq25rd63bhjhctf6gdyrh74gi

PSCR: a coherence protocol for eliminating passive sharing in shared-bus shared-memory multiprocessors

R. Giorgi, C.A. Prete
1999 IEEE Transactions on Parallel and Distributed Systems  
Shared-bus shared-memory multiprocessor can be used to speed-up the execution of such workload.  ...  The copies due to passive sharing produce useless coherence traffic on the bus and coping with such a problem may represent a challenging design problem for these machines.  ...  Two new WU protocols have been defined for two special bus-based machines: on-chip multiprocessor [64] and bus-based COMA [41] .  ... 
doi:10.1109/71.780868 fatcat:c44pju2v5fgm3ozmltso7pz2nu

The Scalable Coherent Interface (SCI)

D.B. Gustavson, Qiang Li
1996 IEEE Communications Magazine  
There is rapidly increasing demand for very-high-performance networked communication for workstation clusters, distributed databases, multiprocessors, industrial data acquisition and control systems, shared  ...  This article first reviews the general properties that an appropriate system architecture should have, and introduces an architectural model, the Local Area MultiProcessor, distinguished by i t s shared-memory  ...  The caches may also significantly rcduce the intcrcotinect traffic. COMA COMA stands for cache-only memory architecture.  ... 
doi:10.1109/35.533919 fatcat:icmnbvnsfffv7hzxejen5fd77m

Parallel Dispatch Queue: a queue-based programming abstraction to parallelize fine-grain communication protocols

B. Falsafi, D.A. Wood
1999 Proceedings Fifth International Symposium on High-Performance Computer Architecture  
In this paper, we study PDQ's impact on software protocol performance in the context of fine-grain distributed shared memory (DSM) on an SMP cluster.  ...  Simulation results running shared-memory applications indicate that: (i) parallel software protocol execution using PDQ significantly improves performance in fine-grain DSM, (ii) tight integration of PDQ  ...  Real data sets also typically do not fit in caches and produce additional memory traffic on the bus.  ... 
doi:10.1109/hpca.1999.744362 dblp:conf/hpca/FalsafiW99 fatcat:hrkgiidfmzc43m4jz2qttnrdpm

Comparing the effectiveness of fine-grain memory caching against page migration/replication in reducing traffic in DSM clusters

An-Chow Lai, Babak Falsafi
2000 Proceedings of the twelfth annual ACM symposium on Parallel algorithms and architectures - SPAA '00  
In this paper, we compare and contrast page migration/replication and R-NUMA on simulated clusters of symmetric multiprocessors executing shared-memory applications.  ...  In this paper, we compare and contrast two techniques to improve capacity/conflict miss traffic in CC-NUMA DSM clusters.  ...  Each node is a 4way multiprocessor with 600 MHz dual-issue processors interconnected by a 100 MHz split-transaction bus.  ... 
doi:10.1145/341800.341811 dblp:conf/spaa/LaiF00 fatcat:xpdbdm5wmfcctazvqt2h476h5u

Optimizing Traffic in DSM Clusters: Fine-Grain Memory Caching versus Page Migration/ Replication

An-Chow Lai, Babak Falsafi
2002 Theory of Computing Systems  
In this paper, we compare and contrast page migration/replication and R-NUMA on simulated clusters of symmetric multiprocessors executing shared-memory applications.  ...  In this paper, we compare and contrast two techniques to improve capacity/conflict miss traffic in CC-NUMA DSM clusters.  ...  Each node is a 4way multiprocessor with 600 MHz dual-issue processors interconnected by a 100 MHz split-transaction bus.  ... 
doi:10.1007/s00224-002-1054-6 fatcat:dc7x2u6svzh55of3u2s3s6reim

Using Symmetric Multiprocessor Architectures for High Performance Computing Environments

Mohsan Tanveer, M. Aqeel Iqbal, Farooque Azam
2011 International Journal of Computer Applications  
In this research paper such kind of critical design aspects of symmetric multi processors have been analyzed for further enhancement of the existing technology.  ...  Symmetric multiprocessor is one of the modern architectures used to perform extensive computations. Symmetric multiprocessors have many configuration modes to carry out these heavy computations.  ...  If we apply lock to Cache, no unrelated bus traffic disturbance is expected.  ... 
doi:10.5120/3332-4582 fatcat:a3z2z33hofc3hj43iigvyovxna

Distributed shared memory: concepts and systems

J. Protic, M. Tomasevic, V. Milutinovic
1996 IEEE Parallel & Distributed Technology Systems & Applications  
His research interests are computer architectures, multiprocessor systems, and distributed shared-memory systems. He can be reached a t etomasev@ubbg.etf.bg.ac.yu.  ...  She is currently working toward her PhD in the field of DSM. Her research interests are in computer architecture, distributed systems, and performance analysis.  ...  We also want to thank Vojislav Protiit for his help in providing up-to-date literature, and Liviu Iftode, who kindly provided some of his most recent papers.  ... 
doi:10.1109/88.494605 fatcat:56jusk7vobepvhcvroadujiiae

A quantitative analysis of the performance and scalability of distributed shared memory cache coherence protocols

M. Heinrich, V. Soundararajan, J. Hennessy, A. Gupta
1999 IEEE transactions on computers  
Existing commercial implementations use a variety of different protocols including bit-vector/coarse-vector protocols, SCI-based protocols, and COMA protocols.  ...  Scalable cache coherence protocols have become the key technology for creating moderate to large-scale sharedmemory multiprocessors.  ...  The availability of cache coherence, and hence software compatibility with smallscale bus-based machines, popularized the commercial use of DSM machines for scalable multiprocessors. A.  ... 
doi:10.1109/12.752662 fatcat:kforuwbdtbfmnarn7uqmivan2a

DDM-a cache-only memory architecture

E. Hagersten, A. Landin, S. Haridi
1992 Computer  
We thank our many colleagues involved in or associated with the project, especially David H.D. Warren of the Universitv of Bristol, who is a coinventor of DDM.  ...  MLkael Lofgren of the Swedish Institute of Computer Science wrote the DDM simulator, basing his work on "Abstract Execution," which was provided to us by James Larus of the University of Wisconsin.  ...  multiprocessor without physically shared memory.  ... 
doi:10.1109/2.156381 fatcat:yzhknrjczze3rn7galuwhf42dy

Page 619 of IEEE Transactions on Computers Vol. 52, Issue 5 [page]

2003 IEEE Transactions on Computers  
Nayfeh and Olukotun [22] study the performance of a cluster-based multiprocessor architecture for various processor-cache configurations in which processors within a cluster are tightly coupled via a shared  ...  Moga and Dubois [20] explore the use of small SRAM network caches as a means to reduce the remote stalls and capacity traffic of multi- allocated in remote processor clusters.  ... 
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