Filters








7,080 Hits in 6.7 sec

Organic Chip Packaging Technology For High Speed Processor Applications

Bernd Garben, Andreas Huber, Dierk Kaller, Erich Klink
2002 Proceedings: 6th IEEE Workshop on Signal Propagation on Interconnects  
In addition different applications for single-chip and multi-chip modules are discussed  SPI 2002 119 0-7803-9821-1/02/$10.00 2002 IEEE  ...  Due to the high dense wiring structures in the build up layers and newly also in the laminated core, high signal I/O applications and dense chip area array footprints can be supported.  ...  This is achieved with a detailed system timing and coupled noise analysis including all coupling segments along the lines.  ... 
doi:10.1109/spi.2002.258316 fatcat:4sx7gizqonhiblpjwfexsf652e

A Thermal Management System for Building Block Computing Systems

Yu Fujita, Kimiyoshi Usami, Hideharu Amano
2014 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs  
Cube-1 is a heterogeneous multiprocessor consisting of 3D stacked chips connecting with inductive coupling through chip interface (TCI).  ...  Unlike TSV which can be used for heat dissipation, stacked chips are electrically contact-less in inductive coupling TCI.  ...  Building block computational systems [1] can tailor a system for each requirement by stacking various types of chips with inductive coupling through-chip interface (TCI).  ... 
doi:10.1109/mcsoc.2014.32 dblp:conf/mcsoc/FujitaUA14 fatcat:6lmxtdopubej5duu2yzvlnwxg4

Design and Integration of All-Silicon Fiber-Optic Receivers for Multi-Gigabit Chip-to-Chip Links

P. Muller, Y. Leblebici, M. Emsley, M. Unlu, A. Tajalli, M. Atarodi
2006 Proceedings of ESSCIRC  
From the system-level requirements, we determine the optimum block-level specifications, based on which the individual building blocks are designed.  ...  This proof of concept is the first step towards design optimized, completely integrated, multi-channel optical receivers for high-bandwidth short-distance chip-to-chip interconnects. I.  ...  The second reason is the goal to analyze potential magnetic coupling between neighboring channels using inductive peaking amplifiers.  ... 
doi:10.1109/esscir.2006.307494 fatcat:76f77nbz6ndxnkupojufyqum7u

Headfirst sliding routing: A time-based routing scheme for bus-NoC hybrid 3-D architecture

Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2013 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS)  
communicate each other wirelessly using inductive-coupling technology.  ...  To simplify the vertical communication interfaces, static Time Division Multiple Access (TDMA) is used for the vertical broadcast buses, while arbitrary or customized topologies can be used for intra-chip  ...  Inductive-coupling has potential as an interconnection technology for custom building-block SiPs, since addition, removal, and swapping of chips become possible after the chips have been fabricated and  ... 
doi:10.1109/nocs.2013.6558406 dblp:conf/nocs/KagamiMKA13 fatcat:6ekg4apexbfnxcdnpqptn74znq

Optical hybrid package with an 8-channel 18GT/s CMOS transceiver for chip-to-chip optical interconnect

E. Mohammed, J. Liao, A. Kern, D. Lu, H. Braunisch, T. Thomas, S. Hyvonen, S. Palermo, I. A. Young, Alexei L. Glebov, Ray T. Chen
2008 Photonics Packaging, Integration, and Interconnects VIII  
The waveguides, which are terminated with multi-terminal (MT) fiber optic connectors, couple out/in highspeed optical signals to/from the chip.  ...  The CMOS drivers and receivers on the transceiver chip and the optical components (VCSEL and Photodiode arrays) are electrically coupled using a short transmission line routed on the top surface of the  ...  ACKNOWLEDGMENTS The authors would like to thank Douglas Stunkard and Julie Mckenney for chip layout design and Bent Danielson for test board layout design.  ... 
doi:10.1117/12.764001 fatcat:kzf3ek7l2vcwtpobfflfsxyan4

A Versatile SoC/SiP Sensor Interface for Industrial Applications: Implementation Challenges

Mohamed Ali, Ahmad Hassan, Mohammad Honarparvar, Morteza Nabavi, Yves Audet, Mohamad Sawan, Yvon Savaria
2022 IEEE Access  
Also, it includes low-voltage blocks like programmable gain amplifiers and ADCs. In addition, DC-to-DC converters are used to supply the various building blocks of the projected sensor interface.  ...  INDEX TERMS Industrial applications, sensor interface, versatility, system-on-chip (SoC), system-inpackage (SiP), thermal management.  ...  SENSOR INTERFACE BUILDING BLOCKS In the following subsections, we present the role, design considerations, and implementation challenges of each building block of the proposed interface.  ... 
doi:10.1109/access.2022.3152379 fatcat:i5ut2mxcq5hwdneep6k2k6y35y

Advance in silicon phased-array receiver IC's

F.E. van Vliet, E.A.M. Klumperink, M.C.M. Soer, S.K. Garakoui, A. de Boer, A.P. de Hek, W. de Heij, B. Nauta
2012 2012 IEEE/MTT-S International Microwave Symposium Digest  
Phased-Arrays are increasingly used, and require Silicon implementations to result in affordable multi-beam systems.  ...  Dynamic range and flexibility of use were the main driving factors.  ...  For current sub-THz power generation systems, this technique is en vogue again, and their building blocks are being demonstrated [2] .  ... 
doi:10.1109/mwsym.2012.6259603 fatcat:5uq4x7upybcmhikltts6ojeefe

Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor

Dac Pham, Atsushi Kameyama, John Keaty, Bob Le, Sang Lee, Tuyen Nguyen, John Petrovick, Mydung Pham, Juergen Pille, Stephen Posluszny, Mack Riley, Hans-Werner Anderson (+11 others)
2006 Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06  
This paper then describes the details behind the design methodology that was used to successfully implement a first-generation CELL processor -a multi-core SoC.  ...  Key features of this methodology are broad optimization with fast rule-based analysis engines using macrolevel abstraction for constraints propagation up/down the design hierarchy, coupled with accurate  ...  Clock Distribution The chip contains three distinct clock distribution systems, each sourced by an independent PLL, to support processor, bus interface, and memory interface requirements.  ... 
doi:10.1145/1118299.1118497 fatcat:ijuxxmwlyba7neqnj7fdnp26ee

Recent Advances in Neural Recording Microsystems

Benoit Gosselin
2011 Sensors  
These emerging tools have revealed a tremendous potential for the advancement of knowledge in brain research and for the development of useful clinical applications.  ...  The accelerating pace of research in neuroscience has created a considerable demand for neural interfacing microsystems capable of monitoring the activity of large groups of neurons.  ...  In such a link, a power amplifier drives an external coil (the primary) to deliver energy to an implanted coil (the secondary) through inductive coupling.  ... 
doi:10.3390/s110504572 pmid:22163863 pmcid:PMC3231370 fatcat:vxz7aqtrpvgnhpv6p36uwp5b3m

A 1.5GHz third generation itanium® 2 processor

Jason Stinson, Stefan Rusu
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Results from the full-chip runs are then "rolled-down" to the block level as interface timing specs.  ...  Timing validation is done using hierarchical static timing analysis tools. To build a full timing model, the design is broken into two basic hierarchies: block and full-chip levels.  ... 
doi:10.1145/775832.776011 dblp:conf/dac/StinsonR03 fatcat:5i7omoozazf53actcdhfxax2u4

A 1.5GHz third generation itanium® 2 processor

Jason Stinson, Stefan Rusu
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Results from the full-chip runs are then "rolled-down" to the block level as interface timing specs.  ...  Timing validation is done using hierarchical static timing analysis tools. To build a full timing model, the design is broken into two basic hierarchies: block and full-chip levels.  ... 
doi:10.1145/776008.776011 fatcat:zuuspfp66zc6phsdjx4klegcvm

Cost and Performance Tradeoff Analysis in Radio and Mixed-Signal System-on-Package Design

L.-R. Zheng, X. Duo, M. Shen, W. Michielsen, H. Tenhunen
2004 IEEE Transactions on Advanced Packaging  
It thus provides a complete picture of quantitative tradeoffs for using on-chip or off-chip passives.  ...  The analysis and modeling techniques explore tradeoffs between performance, cost, robustness, and yield when different on-chip or off-chip passives are used.  ...  Besides, it should be noticed that in order to improve design accuracy, part of package parasitics must be absorbed through chip-package co-design of the circuit building block.  ... 
doi:10.1109/tadvp.2004.828818 fatcat:4aiwwuz6yvhibnjv27oesjapr4

Design, fabrication, and packaging of an integrated, wirelessly-powered optrode array for optogenetics application

Ki Yong Kwon, Hyung-Min Lee, Maysam Ghovanloo, Arthur Weber, Wen Li
2015 Frontiers in Systems Neuroscience  
The design of this system is scalable and its manufacturing is cost effective through batch fabrication using microelectromechanical systems (MEMS) technology.  ...  An integrated, implantable, switched-capacitor based stimulator (SCS) system provides high instantaneous power to the µLEDs through an inductive link to emit sufficient light and evoke neural activities  ...  Building on the device development, most recently we have implemented a wireless neural interface system.  ... 
doi:10.3389/fnsys.2015.00069 pmid:25999823 pmcid:PMC4422027 fatcat:2pl7ukwxdfajdnwihwdwnpveoe

Readout of two-kilopixel transition-edge sensor arrays for Advanced ACTPol [article]

Shawn W. Henderson, Jason R. Stevens, Mandana Amiri, Jason Austermann, James A. Beall, Saptarshi Chaudhuri, Hsiao-Mei Cho, Steve K. Choi, Nicholas F. Cothard, Kevin T. Crowley, Shannon M. Duff, Colin P. Fitzgerald, Patricio A. Gallardo (+19 others)
2016 arXiv   pre-print
The multichroic detector pixels in each array use separate channels for each polarization and each of the two frequencies, such that four TESes must be read out per pixel.  ...  Challenges addressed include doubling the number of detectors per multiplexed readout channel compared to ACTPol and optimizing the Nyquist inductance to minimize detector and SQUID noise aliasing.  ...  Nyquist inductance optimization The signal from each TES in the array is routed through an interface chip before being inductively coupled into a SQ1.  ... 
arXiv:1607.06064v1 fatcat:ncqqhuu6yvdbfmpmaks54wftya

A Fully Integrated 20-Gb/s Optoelectronic Transceiver Implemented in a Standard 0.13-$\mu{\hbox {m}}$ CMOS SOI Technology

Behnam Analui, Drew Guckenberger, Daniel Kucharski, Adithyaram Narasimha
2006 IEEE Journal of Solid-State Circuits  
A dual-channel 10 Gb/s per channel single-chip optoelectronic transceiver has been demonstrated in a 0.13-m CMOS SOI technology.  ...  Such a high level of optoelectronic integration is unprecedented, and serves to substantially reduce system footprint and power dissipation, allowing efficient scaling to higher data rates and broader  ...  SYSTEM BUILDING BLOCKS A. Optical Components 1) Holographic Lens: The ability to couple light in and out of the silicon chip efficiently is essential to the silicon photonics approach.  ... 
doi:10.1109/jssc.2006.884388 fatcat:hqp2z6ylnffnthgm3szcjpw3ve
« Previous Showing results 1 — 15 out of 7,080 results