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Bridging the computation gap between programmable processors and hardwired accelerators

Kevin Fan, Manjunath Kudlur, Ganesh Dasika, Scott Mahlke
2009 2009 IEEE 15th International Symposium on High Performance Computer Architecture  
The efficiency of the programmable accelerator is compared with non-programmable accelerators and with the OpenRISC 1200 general purpose processor.  ...  The programmable accelerator is able to achieve up to 34x better power efficiency and 30x better area efficiency than a simple general purpose processor, while trading off as little as 2x power and area  ...  Acknowledgements We wish to extend our thanks to Shantanu Gupta, Shuguang Feng, and Jason Blome for their help synthesizing the OR-1200 processor.  ... 
doi:10.1109/hpca.2009.4798266 dblp:conf/hpca/FanKDM09 fatcat:j6fturcuangelcvqx6iwgbb2ve

Wireless platforms

Francine Bacchini, Jan Rabaey, Allan Cox, Frank Lane, Rudi Lauwereins, Ulrich Ramacher, David Witt
2005 Proceedings of the 42nd annual conference on Design automation - DAC '05  
In response to these challenges, many solutions have been floated and experimented with ranging from multi-processor architectures, advanced DSPs, reconfigurable solutions and hardwired accelerators.  ...  Hierarchical scaling of compute element, processor, micro-interconnect and macrointerconnect are critical factors for success.  ...  The flexibility offered by both solutions facilitates cross layer management of parameters across the complete terminal, bridging the gap between communication and application.  ... 
doi:10.1145/1065579.1065673 dblp:conf/dac/BacchiniRCLLRW05 fatcat:4bfmzq4rcfdidp5j3urs4uek4i

Wireless platforms: GOPS for cents and MilliWatts

F. Bacchini, J. Rabaey, A. Cox, F. Lane, R. Lauwereins, U. Ramacher, D. Witt
2005 Proceedings. 42nd Design Automation Conference, 2005.  
In response to these challenges, many solutions have been floated and experimented with ranging from multi-processor architectures, advanced DSPs, reconfigurable solutions and hardwired accelerators.  ...  Hierarchical scaling of compute element, processor, micro-interconnect and macrointerconnect are critical factors for success.  ...  The flexibility offered by both solutions facilitates cross layer management of parameters across the complete terminal, bridging the gap between communication and application.  ... 
doi:10.1109/dac.2005.193832 fatcat:drppi7vv2vbkzj7h2v5lkuznoe

Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays

Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
2008 2008 Symposium on Application Specific Processors  
The EGRA attempts to further close the performance gap between reconfigurable and hardwired logic by implementing an arithmetic/logic expression per cell, rather than a single operation.  ...  Reconfigurable Arrays combine the benefit of spatial execution, typical of hardware solutions, with that of programmability, present in microprocessors.  ...  The problem of bridging this gap has been the focus of much research in the last decades, and important advances have been made.  ... 
doi:10.1109/sasp.2008.4570782 dblp:conf/sasp/AnsaloniBP08 fatcat:y72l6rz5eng25kmmdf4qu7dcly

Configware and morphware going mainstream

Jürgen Becker, Reiner Hartenstein
2003 Journal of systems architecture  
The paper addresses a broad readership in information technology, computer science and related areas, and gives an introduction to fine grain and coarse grain morphware, reconfigurable computing, and its  ...  Avoiding this memory bottleneck not only by using accelerators, but also by innovative computing architectures, or even by breaking the dominance of the von Neumann machine paradigm is a promising goal  ...  This education gap can be easily bridged only by a curricular transition from the von-Neumann-only mind set toward this dichotomy of two basic computing paradigms, where the vN paradigm is taught together  ... 
doi:10.1016/s1383-7621(03)00073-0 fatcat:ebvbvahp35cdfmymcru6e73yrq

Basics of Reconfigurable Computing [chapter]

Reiner Hartenstein, Tu Kaiserslautern
2007 Designing Embedded Processors  
To bridge the translational gap, the software / configware chasm, we need to think outside the box.  ...  Modern FPGAs as COTS (commodities off the shelf) have all 3 paradigms on board of the same VLSI chip: hardwired accelerators, micro-processors (and memory banks), and FPGAs, and we need both, software  ... 
doi:10.1007/978-1-4020-5869-1_20 fatcat:2uyk5ixupfdorl4ou7apk2q4ra

Efficient software architecture for IPSec acceleration using a programmable security processor

Janar Thoguluva, Anand Raghunathan, Srimat T. Chakradhar
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
reduce the crypto offloading overheads, and (ii) using crypto offloading judiciously based on the trade-off between the savings in processing cycles vs. the overhead of communication with the security  ...  Cryptographic accelerators and security processors are often used in embedded systems in order to enable enhanced security without significantly impacting performance or power consumption.  ...  Acknowledgment: The authors would like to acknowledge Srivaths Ravi and Murugan Sankaradass for useful discussions related to this work.  ... 
doi:10.1145/1403375.1403656 fatcat:qbmj4ajes5hefghj6jrplvaola

The Paramountcy of Reconfigurable Computing [chapter]

Reiner Hartenstein
2012 Energy-Efficient Distributed Computing Systems  
For bridging the translational gap, the software / configware chasm, we need to think outside the box3. Why Computers are Important Computers are very important for all of us.  ...  To obtain the payoff from RC we need a new understanding of computing and supercomputing, as well as of the use of accelerators (section 19.6.3).  ...  Programmers cannot work with hardware description languages like FPGA experts 142 . We have to bridge this gap.  ... 
doi:10.1002/9781118342015.ch18 fatcat:shfb4oycu5hu5boizx6oltlgwa

Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor

Janar Thoguluva, Anand Raghunathan, Srimat T. Chakradhar
2008 2008 Design, Automation and Test in Europe  
reduce the crypto offloading overheads, and (ii) using crypto offloading judiciously based on the trade-off between the savings in processing cycles vs. the overhead of communication with the security  ...  Cryptographic accelerators and security processors are often used in embedded systems in order to enable enhanced security without significantly impacting performance or power consumption.  ...  Acknowledgment: The authors would like to acknowledge Srivaths Ravi and Murugan Sankaradass for useful discussions related to this work.  ... 
doi:10.1109/date.2008.4484833 dblp:conf/date/ThoguluvaRC08 fatcat:2pwrajaayffkleowv6jyxqhbku

A Signal Processor for Gaussian Message Passing [article]

Harald Kröll, Stefan Zwicky, Reto Odermatt, Lukas Bruderer, Andreas Burg, Qiuting Huang
2014 arXiv   pre-print
The results demonstrate the usabilty of the FGP architecture as a flexible HW accelerator for signal-processing and communication systems.  ...  More specifically, the demonstrated factor graph processor (FGP) is tailored to Gaussian message passing algorithms.  ...  Various attempts have been reported to bridge the gap between hardwired accelerators and programmable processors, where the trade-offs between performance and programmability have been subject of many  ... 
arXiv:1404.3162v1 fatcat:q2d42jwya5cpzdbaavnevqbxca

Heterogeneous Multi-core Architectures

Tulika Mitra
2015 IPSJ Transactions on System LSI Design Methodology  
In this context, heterogeneous multi-core architectures combining functionality and performance-wise divergent mix of processing cores (CPU, GPU, special-purpose accelerators, and reconfigurable computing  ...  Heterogeneous multi-cores can potentially provide energy-efficient computation as only the cores most suitable for the current computation need to be switched on.  ...  Reconfigurable computing [14] fills this gap between hardware and software with far superior performance potential compared to programmable cores while maintaining higher-level of flexibility than ASICs  ... 
doi:10.2197/ipsjtsldm.8.51 fatcat:wgiuptlmvvgnhdt2bjrcio6oqi

Observations on Power-Efficiency Trends in Mobile Communication Devices [chapter]

Olli Silvén, Kari Jyrkkä
2005 Lecture Notes in Computer Science  
Computing solutions used in mobile communications equipment are essentially the same as those in personal and mainframe computers.  ...  The key differences between the implementations are found at the chip level: in mobile devices low leakage silicon technology and lower clock frequency are used.  ...  Acknowledgements This paper is based on the contributions of numerous people. In particular, we wish to thank Dr. Lauri Pirttiaho and Prof. Yrjö Neuvo, both from the Nokia Corporation.  ... 
doi:10.1007/11512622_16 fatcat:y657ek2c3ve5pjsnm5d2bouq6m

Observations on Power-Efficiency Trends in Mobile Communication Devices

Olli Silven, Kari Jyrkkä
2007 EURASIP Journal on Embedded Systems  
Computing solutions used in mobile communications equipment are essentially the same as those in personal and mainframe computers.  ...  The key differences between the implementations are found at the chip level: in mobile devices low leakage silicon technology and lower clock frequency are used.  ...  Acknowledgements This paper is based on the contributions of numerous people. In particular, we wish to thank Dr. Lauri Pirttiaho and Prof. Yrjö Neuvo, both from the Nokia Corporation.  ... 
doi:10.1155/2007/56976 fatcat:qaf74xxzdjf6bcrwxxkhvqsqlm

Observations on Power-Efficiency Trends in Mobile Communication Devices

Olli Silven, Kari Jyrkkä
2007 EURASIP Journal on Embedded Systems  
Computing solutions used in mobile communications equipment are essentially the same as those in personal and mainframe computers.  ...  The key differences between the implementations are found at the chip level: in mobile devices low leakage silicon technology and lower clock frequency are used.  ...  Acknowledgements This paper is based on the contributions of numerous people. In particular, we wish to thank Dr. Lauri Pirttiaho and Prof. Yrjö Neuvo, both from the Nokia Corporation.  ... 
doi:10.1186/1687-3963-2007-056976 fatcat:4vu54id7nfdjtdbohhkyr7p55e

The design of dynamically reconfigurable datapath coprocessors

Zhining Huang, Sharad Malik, Nahri Moreano, Guido Araujo
2004 ACM Transactions on Embedded Computing Systems  
The programmability comes with a power and performance overhead.  ...  These programmable platforms span a large range from bit-level programmable field programmable gate arrays to word-level programmable application-specific, and in some cases even general-purpose processors  ...  These processors bridge the ASIC-GPP gap by adding the efficiency of ASICs to the flexibility of GPPs.  ... 
doi:10.1145/993396.993403 fatcat:74rhii2ksvdubggcky4fsx4a6q
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