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Branch Optimisation Techniques for Hardware Compilation
[chapter]
2003
Lecture Notes in Computer Science
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A hardware compilation system has been developed for producing designs which are optimised for different branch probabilities. ...
For designs of equal performance, branch-optimised designs require 24% and 27.5% less area. For designs of equal area, branch optimised designs run upto 3 times faster. ...
Conclusion This paper explores using branch probability information to optimise hardware compilation. ...
doi:10.1007/978-3-540-45234-8_32
fatcat:fmtjt6xwlzbudg25ly2txjcbre
Identifying Compiler Options to Minimize Energy Consumption for Embedded Platforms
2013
Computer journal
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2013 pre-print arXiv:1303.6485v1 fatcat:7whw2ip7ubawhlm73swr6ldczaOther Versions
This paper presents an analysis of the energy consumption of an extensive number of the optimisations a modern compiler can perform. ...
A further conclusion of this study is the structure of the benchmark has a larger effect than the hardware architecture on whether the optimisation will be effective, and that no single optimisation is ...
An analysis of the techniques the compiler can perform to optimise for energy was carried out by Tiwari, Malik and Wolfe [19] . ...
doi:10.1093/comjnl/bxt129
fatcat:tv4ltx5hjzc7teaatnw4wg5z7m
Declarative peephole optimization using string pattern matching
1999
SIGPLAN notices
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Peephole optimisation as a last step of a compilation sequence capitalises on significant opportunities for removing low level code slackness left over by the code generation process. ...
optimum branch instructions according to the program's branch behaviour. ...
A comparison of software and hardware schemes for reducing the cost of branches can be found in [HCC89] . ...
doi:10.1145/307903.307921
fatcat:kgpxqqr7erft5p3wvfihqqhwz4
Application-specific customisation of multi-threaded soft processors
2006
IEE Proceedings - Computers and digital Techniques
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Custom instructions, optimised for a specific application, accelerate frequently performed computations by implementing them as dedicated hardware. ...
CUSTARD features include design space exploration and a compiler for automatic selection of custom instructions. ...
Acknowledgments We gratefully acknowledge the support of ACE Associated Compiler Experts, Celoxica, the EPSRC and Xilinx. ...
doi:10.1049/ip-cdt:20050177
fatcat:sxvw5bqkrnbt3focyztuxn4y5q
Data distribution at run-time: Re-using execution plans
[chapter]
1998
Lecture Notes in Computer Science
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We have adapted both conventional parallelising compiler techniques and hardware dynamic branch prediction techniques in order to ensure that our run-time optimisations need not perform any more work than ...
This paper shows how data placement optimisation techniques which are normally only found in optimising compilers can be made available e ciently in run-time systems. ...
We thank the Imperial College Parallel Computing Centre for the use of their AP3000 machine. ...
doi:10.1007/bfb0057884
fatcat:kicqatzb7nd7zjh7wpn6w7wmt4
Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation
2008
International Journal of Reconfigurable Computing
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Both optimisations operate on a high-level program representation and have been implemented in a commercial SystemC compiler. ...
Experiments show that in suitable circumstances these techniques result in significant reductions in logic utilisation for FPGAs. ...
The second optimisation technique automatically maps arrays in SystemC to multiport memories in hardware. ...
doi:10.1155/2008/674340
fatcat:jbrlditudvgdlp577rbebj6fku
Branch merging for scheduling concurrent executions of branch operations
1996
IEE Proceedings - Computers and digital Techniques
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The authors study the problem of compile-time scheduling of branch operations on such architectures: an optimisation called branch merging. ...
The scheduling attempts to bring profitable branches together for concurrent execution. It is shown that finding the optimal solution to the branch merging problem is NPhard. ...
The problem is that applying these optimisation techniques tends to cluster branches together [ 131 and increase the relative frequency of branches in the instruction stream [ 151 [Note 11. ...
doi:10.1049/ip-cdt:19960822
fatcat:na5hcyvcbbh2pm5kgaksldix7u
Machine Learning in Compiler Optimisation
[article]
2018
arXiv
pre-print
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In this article, we describe the relationship between machine learning and compiler optimisation and introduce the main concepts of features, models, training and deployment. ...
We then provide a comprehensive survey and provide a road map for the wide variety of different research areas. ...
Branch instructions
#conditional branch instr, #uncon-
ditional branch instr
loop information
#loops, loop depth
parallel information
#work threads, work group size
01010
Program binary
Hardware ...
arXiv:1805.03441v1
fatcat:bhd7mpl6lzaedbuy7iln4hntki
Correct, fast, maintainable
2012
Proceedings of the Asia-Pacific Workshop on Systems - APSYS '12
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We present our techniques in modifying the C sources to assist with compiler optimisation. ...
We present a case study of optimising the IPC fastpath in the seL4 microkernel. This fastpath is written in C and relies on an optimising C compiler for good performance. ...
Acknowledgements We thank James Wilmot for his assistance with benchmarking seL4's IPC fastpaths. ...
doi:10.1145/2349896.2349909
dblp:conf/apsys/BlackhamH12
fatcat:hnkuzcni2nhwxabqcus3xwks44
A Statically Allocated Parallel Functional Language
[chapter]
2000
Lecture Notes in Computer Science
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The motivation behind SAFL is hardware description and synthesis-we have built an optimising compiler for translating SAFL to silicon. ...
for argument and return values). ...
Acknowledgments We are indebted to Neil Jones, Martin Hofmann, Simon Peyton-Jones and the anonymous referees for comments which have improved this paper. ...
doi:10.1007/3-540-45022-x_5
fatcat:t4q5dpulzjcyznnrmyjv2dwueq
A Study on the Influence of Software and Hardware Features on Program Energy
2016
Proceedings of the 10th ACM/IEEE International Symposium on Empirical Software Engineering and Measurement - ESEM '16
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, characteristics of the program and the workload running, OS routines, compiler optimisations, among others. ...
We collected over 100 hardware and software metrics, statically and dynamically, using existing tools for program analysis, instrumentation and run time monitoring. ...
Existing optimisation techniques targeting performance may also be adequate for energy. ...
doi:10.1145/2961111.2962593
dblp:conf/esem/RajanNS16
fatcat:gyslcrv4tjeklbxtucmxfl5kcu
Reconfigurable computing: architectures and design methods
2005
IEE Proceedings - Computers and digital Techniques
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Reconfigurable computing is becoming increasingly attractive for many applications. This survey covers two aspects of reconfigurable computing: architectures and design methods. ...
It is shown that reconfigurable computing designs are capable of achieving up to 500 times speedup and 70% energy savings over microprocessor implementations for specific applications. ...
A hardware compiler has been developed to produce a collection of designs, each optimised for a particular branch probability; the best can be selected at runtime by incorporating observed branch probability ...
doi:10.1049/ip-cdt:20045086
fatcat:rz53tnd6yfd7heyk5qhvaj5jfu
Flexible instruction processors
2000
Proceedings of the international conference on Compilers, architectures, and synthesis for embedded systems - CASES '00
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strategies involving standard compilers and FIP-specific compilers, and the associated design flow; (d) technology-independent and technology-specific optimisations, such as techniques for efficient resource ...
Our current implementation of the FIP framework is based on a highlevel parallel language called Handel-C, which can be compiled into hardware. ...
strategies involving standard compilers and FIP-specific compilers, and the associated design flow; (d) technologyindependent and technology-specific optimisations, such as techniques for efficient resource ...
doi:10.1145/354880.354907
dblp:conf/cases/SengLC00
fatcat:y3wswp5t4jdmpekua743klwkl4
Page 109 of Journal of Research and Practice in Information Technology Vol. 28, Issue 3
[page]
1996
Journal of Research and Practice in Information Technology
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This book describes several techniques to tailor compilers to take maximum advantage of the capabilities of the hardware while reducing its cost and to tailor hardware to the characteristics and limitations ...
The first paper describes a technique called boosting that matches the capabilities of the hardware and of the compiler in a very nice way, and examines several system designs of varying complexity that ...
A hardware mechanism to reduce the energy consumption of the register file of in-order architectures
2008
International Journal of Embedded Systems
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His research interests are hardware and systems, including building computer systems, computer architecture, and compiler design. ...
This technique achieves an 85% energy reduction with no performance penalty. Keywords: register file; in-order; power reduction; predecode; hardware approach. ...
Many recent compiler optimisation techniques increase the register pressure, and there is a current trend towards implementing larger register files. ...
doi:10.1504/ijes.2008.022400
fatcat:23nzw4e6yrb4tlrhzdwkyuqgzm
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