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Bounds on the complexity of recurrent neural network implementations of finite state machines

Bill G. Horne, Don R. Hush
1996 Neural Networks  
In this paper the efficiency of recurrent neural network implementations of m-state finite state machines will be explored.  ...  Matching lower bounds will be provided for each of these upper bounds assuming that the state of the FSM can be encoded in a subset of the nodes of size rlog m 1.  ...  In the same paper lower bounds on node complexity were investigated as the network was subject to restrictions on the possible range of weight values and the fan-in and fan-out of the nodes in the network  ... 
doi:10.1016/0893-6080(95)00095-x fatcat:rz5a7jp3cze25bommdiuaujzj4

2-1 addition and related arithmetic operations with threshold logic

S. Vassilladis, S. Cotofana, K. Bertels
1996 IEEE transactions on computers  
For existing architectural formats we show that our schemes, with equal or smaller depth networks, substantially outperform existing schemes in terms of size and fan-in requirements and in occasions in  ...  For n bit operands we propose a depth-3 O( n 2 log n ) asymptotic size network for the binary addition with polynomially bounded weights.  ...  Therefore the weights are at most 2 d p n e and the maximum fan-in is upper bounded by 2d p n e + 1.  ... 
doi:10.1109/12.537130 fatcat:n4xucwzx7ne4jn6tjjj7imr7oa

A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic

K.S. Lowe, P.G. Gulak
1998 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In this way, high drive capability buffered (i.e., BiCMOS) gates with sufficiently low fan-out are identified and replaced with a lower power unbuffered (i.e., CMOS) version.  ...  This paper presents the first reported joint gate sizing and buffer insertion method for minimizing the delay of power constrained combinational logic networks that can incorporate a mixture of unbuffered  ...  Finally, typical relationships between optimized delay and external load (i.e., network fan-out) are plotted in Fig. 11 .  ... 
doi:10.1109/43.703932 fatcat:wvs2nmma7zddrpxm2bmvlvvwb4

Page 1534 of Mathematical Reviews Vol. 56, Issue 4 [page]

1978 Mathematical Reviews  
The first set of results concerns combinational circuits with fan-out fand fan-in 2; e.g., an e way fan-out can be accomplished using gates with fan-out of f>2 in a delay time less than or equal to flog  ...  These tesults can give realistic time delay and gate bounds for useful circuits; e.g., a 16 pin integrated circuit using gates with fan-in 2 and fan-out 8 can be designed with a total package time delay  ... 

Page 736 of Mathematical Reviews Vol. 55, Issue 2 [page]

1978 Mathematical Reviews  
Author’s summary: “An algorithm for finding a minimal set of single fault detection tests in logical combinational irredundant many-level fan-out networks is presented in this paper.  ...  Such equations arise in composing economical plans. R. Shirtladze (Tbilisi) Nguyen Xuan Quynh 5317 An algorithm for fault detection in logical combinational many- level fan-out networks.  ... 

Page 1551 of Mathematical Reviews Vol. 57, Issue 4 [page]

1979 Mathematical Reviews  
These upper bounds are generally poor for networks with fan-out.  ...  Algorithms to synthesize a fan-out-free network for a given function and methods to detect multiple faults and to locate single faults in ar- bitrary fan-out-free networks are developed.  ... 

Page 1826 of Mathematical Reviews Vol. 48, Issue 5 [page]

1974 Mathematical Reviews  
Addi- tionally, no signal in the circuit fans out to more than some bounded number of terminals where the bound depends only on the module being used. Two different realization 10701 CC al S,.  ...  Newborn, Monroe M.; Arnold, Thomas F. 10702 Universal modules for bounded signal fan-out synchro- nous sequential circuits. IEEE Trans. Computers C-21 (1972), 63—79.  ... 

Post-layout logic duplication for synthesis of domino circuits with complex gates

Aiqun Cao, Ruibing Lu, Cheng-Kok Koh
2005 Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05  
Logic duplication to resolve the logic reconvergent paths problem encountered in Domino logic synthesis is expensive in terms of area and power.  ...  In this paper, we propose a combined logic duplication minimization and technology mapping scheme for Domino circuits with complex gates.  ...  In order to implement a binate logic network by a Domino circuit, which can only implement non-inverting logic, the binate logic network has to be transformed into a unate one by pushing inverters (bubble  ... 
doi:10.1145/1120725.1120845 dblp:conf/aspdac/CaoLK05 fatcat:taufexay5naktgx3whoh5bbpzy

PHOTONIC SWITCHING IN COMMUNICATIONS SYSTEMS

H. S. HINTON
1988 Le Journal de Physique Colloques  
This paper will review some potential applications of optical logic devices. It will focus on a system that is based on perfect shuffle optical interconnects.  ...  These two equations imply that for a large fan-out and fan-in, which is desirable, a large sharp nonlinearity is required.  ...  Another problem associated with the critically biased devices that have been previously described is the size of the fan-in and the fan-out of the device.  ... 
doi:10.1051/jphyscol:1988202 fatcat:uydfx24y35ce7jha34od7553xq

Page 1867 of Mathematical Reviews Vol. , Issue 98C [page]

1998 Mathematical Reviews  
, Robert C. (5-ANU-EG; Canberra) Efficient agnostic learning of neural networks with bounded fan-in.  ...  The networks we consider have real-valued inputs and outputs, an unlimited number of threshold hidden units with bounded fan-in, and a bound on the sum of the absolute values of the output weights.  ... 

An Optimized Fuzzy Logic Control Model Based on a Strategy for the Learning of Membership Functions in an Indoor Environment

Muhammad Fayaz, Israr Ullah, DoHyeun Kim
2019 Electronics  
In the CA module, the Mamdani FLC method has been used, whereas, in the LA module, we have used the artificial neural network (ANN) algorithm.  ...  Inputs into the fuzzy logic controller (FLC) were the error difference between environmental temperature and required temperature (D), and the output was the required power for the fan actuator.  ...  The neural network implementation was also carried out in MATLAB.  ... 
doi:10.3390/electronics8020132 fatcat:vfvhrusrwzfkpoak6wgqy2yzpe

Page 1218 of Mathematical Reviews Vol. 57, Issue 3 [page]

1979 Mathematical Reviews  
If we additionally require that the amount of equip- ment of the resulting network be bounded by a linear function of n, it is possible to bound the depth by 2 log. n with a fan-in of at most 3.” ~ R.  ...  In particular, an algorithm for detecting all faults occurring at every input and at branches of every fan-out gate is considered in detail.  ... 

Postlayout optimization for synthesis of Domino circuits

Aiqun Cao, Ruibing Lu, Chen Li, Cheng-Kok Koh
2006 ACM Transactions on Design Automation of Electronic Systems  
In this article, we propose a synthesis scheme to reduce the duplication cost by allowing inverters in Domino logic under certain timing constraints for both simple and complex gates.  ...  In order to guarantee the robustness of such Domino circuits, we perform the logic optimization as a postlayout step.  ...  The inverters were allowed in the logic network by synthesizing the transitive fan-outs of the inverters into static CMOS logic.  ... 
doi:10.1145/1179461.1179462 fatcat:tdac5cexkfgtbmuzzw7xdiiceu

Page 818 of Mathematical Reviews Vol. 47, Issue 3 [page]

1974 Mathematical Reviews  
Hence our results can be readily extended to those generalized networks as long as all input and output switches have fan-out fan-in capability.  ...  By introducing the concept of error vectors that indicate how the effect of a fault propagates through a logic network, the author presents a number of properties of fault detection in linear logic networks  ... 

Page 4944 of Mathematical Reviews Vol. , Issue 99g [page]

1999 Mathematical Reviews  
, CA) Bounded fan-out multimessage multicasting.  ...  We assume for simplicity that each combinational element has bounded fan-in and fan-out and can be evaluated in constant time.  ... 
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