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Insertion and promotion for tree-based PseudoLRU last-level caches

Daniel A. Jiménez
2013 Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture - MICRO-46  
Last-level caches mitigate the high latency of main memory. A good cache replacement policy enables high performance for memory intensive programs.  ...  It has slightly less than one bit of overhead per cache block, compared with two or more bits per cache block for competing policies.  ...  I would also like to thank Yale Patt who, in a happy coincidence, happened to show up to a somewhat randomly scheduled talk I gave based on this research in Spain.  ... 
doi:10.1145/2540708.2540733 dblp:conf/micro/Jimenez13 fatcat:gv4bmdpjlvgmzfjrlgss36nlde

Dynamic and discrete cache insertion policies for managing shared last level caches in large multicores

Aswinkumar Sridharan, André Seznec
2017 Journal of Parallel and Distributed Computing  
Acknowledgment The authors would like to thank the members of the ALF team for their feedback on this work.  ...  Table 1 : 1 Insertion Priority Summary Priority Level Insertion Value High (HP) 0 Medium (MP) 1 but 1/16th insertion at LP Low (LP) 2 but 1/16th at MP Least (LstP) Bypass but insert 1/32nd at LP  ...  We define this interval in terms of the number of misses at the shared last level cache since only misses trigger new cache blocks to be allocated.  ... 
doi:10.1016/j.jpdc.2017.02.004 fatcat:24hmq6ycqnhhxcmyt2hzaxrmpu

Mac : A Novel Systematically Multilevel Cache Replacement Policy For Pcm Memory

Haixia Shenchen Ruan
2016 Zenodo  
To handle the problem of write, optimizing the cache replacement policy to protect dirty cache block is an efficient way.  ...  In this paper, we construct a systematically multilevel structure, and based on it propose a novel cache replacement policy called MAC.  ...  Among them,optimizing the cache replacement policy of last level cache (LLC) is an effective way. Traditional cache replacement policies are designed for systems using DRAM memory.  ... 
doi:10.5281/zenodo.1199858 fatcat:honlqazqgngfhczxnmknxxkyze

Performance and energy assessment of last-level cache replacement policies

Pierre-Yves Peneau, David Novo, Florent Bruguier, Gilles Sassatelli, Abdoulaye Gamatie
2017 2017 First International Conference on Embedded & Distributed Systems (EDiS)  
The Last-Level Cache (LLC) is a critical component of the memory hierarchy which has a direct impact on performance.  ...  In this paper, we analyze a number of cache replacement policies that have been proposed over the last decade and carry out evaluations reporting performance and energy.  ...  Therefore, an efficient memory system is key to providing compute systems with high performance capabilities. A key component of the memory hierarchy is the Last-Level Cache, or LLC.  ... 
doi:10.1109/edis.2017.8284032 fatcat:shdb4acdqngkdlqtstt4outnlu

WARP: Workload Nature Adaptive Replacement Policy

Balaji S, Gautham Shankar R, Arvind Krishna P
2013 International Journal of Computer Applications  
WARP redesigns the replacement policy in the last level cache.  ...  This performance improvement was solely from the policy implemented on the last level cache and not from any other parameters.  ...  LRU is used as the replacement policy for levels of cache closer to the processor and WARP is restricted only to the last level of cache, so as to improve instructions per clock cycle.  ... 
doi:10.5120/11978-7849 fatcat:7f6yo5p7n5ftferrqekvdusgqm

The evicted-address filter

Vivek Seshadri, Onur Mutlu, Michael A. Kozuch, Todd C. Mowry
2012 Proceedings of the 21st international conference on Parallel architectures and compilation techniques - PACT '12  
We compare our EAF-based mechanism to ve state-of-the-art mechanisms that address cache pollution or thrashing, and show that it provides signi cant performance improvements for a wide variety of workloads  ...  O -chip main memory has long been a bottleneck for system performance. With increasing memory pressure due to multiple onchip cores, e ective cache utilization is important.  ...  We acknowledge members of the SAFARI and LBA groups for their feedback and for the stimulating research environment they provide.  ... 
doi:10.1145/2370816.2370868 dblp:conf/IEEEpact/SeshadriMKM12 fatcat:byttqcggj5hotmdg5vyujcpjli

MAC: a novel systematically multilevel cache replacement policy for PCM memory [article]

Shenchen Ruan, Haixia Wang, Dongsheng Wang
2016 arXiv   pre-print
To handle the problem of write, optimizing the cache replacement policy to protect dirty cache block is an efficient way.  ...  In this paper, we construct a systematically multilevel structure, and based on it propose a novel cache replacement policy called MAC.  ...  Among them, optimizing the cache replacement policy of last level cache (LLC) is an effective way. Traditional cache replacement policies are designed for systems using DRAM memory.  ... 
arXiv:1606.03248v1 fatcat:gnpwoj47jzcmhoihttwg46rnku

Discrete Cache Insertion Policies for Shared Last Level Cache Management on Large Multicores

Aswinkumar Sridharan, Andre Seznec
2016 2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS)  
Multi-core processors employ shared Last Level Caches (LLC). This trend will continue in the future with large multi-core processors (16 cores and beyond) as well.  ...  LLC management policies have been extensively studied for small scale multi-cores (4 to 8 cores) and associativity degree in the 16 range.  ...  ACKNOWLEDGMENT The authors would like to thank the members of the ALF team for their suggestions. This work is partially supported by ERC Advanced Grant DAL No. 267175.  ... 
doi:10.1109/ipdps.2016.30 dblp:conf/ipps/SridharanS16 fatcat:bq2i7o7kn5be7jkhda424erpwe

Addressing Variability in Reuse Prediction for Last-Level Caches [article]

Priyank Faldu
2020 arXiv   pre-print
Last-Level Cache (LLC) represents the bulk of a modern CPU processor's transistor budget and is essential for application performance as LLC enables fast access to data in contrast to much slower main  ...  Once identified, dead blocks are evicted from LLC to make space for potentially high reuse cache blocks.  ...  "Leeway: Addressing Variability in Dead-Block Prediction for Last-Level Caches".  ... 
arXiv:2006.08487v1 fatcat:4stqscurbbcb3am5lw33c4pksm

Partially Shared Cache and Adaptive Replacement Algorithm for NoC-based Many-core Systems

Pengfei Yang, Quan Wang, Hongwei Ye, Zhiqiang Zhang
2019 Journal of systems architecture  
including the URL of the record and the reason for the withdrawal request.  ...  When a cache block is inserted, the insertion policy sets the value of the inserted cache block to 2. The promotional policy is shown in lines 5 and 6 of Figure 6 .  ...  [7] proposed a non-inclusive cache that fully utilized only the last-level cache space for the CMP.  ... 
doi:10.1016/j.sysarc.2019.05.002 fatcat:v2ftf4k3x5ceple2tdcdx44ixm

Relative Performance of a Multi-level Cache with Last-Level Cache Replacement: An Analytic Review [article]

Bijay Paikaray
2013 arXiv   pre-print
Current day processors employ multi-level cache hierarchy with one or two levels of private caches and a shared last-level cache (LLC).  ...  An efficient cache replacement policy at LLC is essential for reducing the off-chip memory transfer as well as conflict for memory bandwidth.  ...  The key idea is to predict a missed block's temporal locality before inserting it into the cache and choose the appropriate insertion policy for the block.  ... 
arXiv:1307.6406v1 fatcat:xswji4f5pzbnfdfg24gygqzoqu

Adaptive Group Based Replace Policy for high peroformance caching

Liqiang He, Yan Sun, Chaozhong Zhang
2010 2010 3rd International Conference on Computer Science and Information Technology  
In ASRP policy, each set in Last-Level Cache (LLC) is divided into multiple subsets, and one subset is active and others are inactive at a given time.  ...  The victim block for a miss is only chosen from the active subset using LRU policy. A counter in each set records the cache misses in the set during a period of time.  ...  In this paper, we first propose a Subset Based Replacement Policy (SRP) for high performance caching.  ... 
doi:10.1109/iccsit.2010.5564500 fatcat:vstrvo4fpnefnmumvxalewmt6a

Small-LRU: A Hardware Efficient Hybrid Replacement Policy

Purnendu Das, Bishwa Ranjan
2020 International Journal of Advanced Computer Science and Applications  
In this policy random replacement is used for 70% ways and LRU is applied for rest of the ways. The early eviction of dead blocks also improves the performance of the system by 5%.  ...  As the demand of data intensive application is increasing it is highly required that the size of the Last Level Cache (LLC) must be increased.  ...  In multi-level cache, the first level cache (L1) is allotted as private cache to individual core whereas the large last level cache (LLC) is shared by all the cores.  ... 
doi:10.14569/ijacsa.2020.0110981 fatcat:dyrh76k575dtbbwzo6xinuz4ia

Pseudo-LIFO

Mainak Chaudhuri
2009 Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture - Micro-42  
However, we observe that as the last-level cache grows in capacity and associativity, the traditional dead block prediction-based replacement policy loses effectiveness because often the LRU block itself  ...  Cache blocks often exhibit a small number of uses during their life time in the last-level cache. Past research has exploited this property in two different ways.  ...  A more recent proposal shows how to design a large, yet fast, victim cache for the last level of caches with selective insertion based on the frequency of misses to different cache blocks [1] .  ... 
doi:10.1145/1669112.1669164 dblp:conf/micro/Chaudhuri09 fatcat:digd6dyfm5gfphjf4zf7jklzmm

Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers

Santhosh Srinath, Onur Mutlu, Hyesoon Kim, Yale N. Patt
2007 2007 IEEE 13th International Symposium on High Performance Computer Architecture  
We also introduce a mechanism that dynamically decides where in the LRU stack to insert the prefetched blocks in the cache based on the cache pollution caused by the prefetcher.  ...  High performance processors employ hardware data prefetching to reduce the negative performance impact of large main memory latencies.  ...  Acknowledgments We thank Matthew Merten, Moinuddin Qureshi, members of the HPS Research Group, and the anonymous reviewers for their comments and suggestions.  ... 
doi:10.1109/hpca.2007.346185 dblp:conf/hpca/SrinathMKP07 fatcat:freouwwyfvf6ljqss2fnj7guii
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