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PCM-2R: Accelerating MLC PCM Writes via Data Reshaping and Remapping
2022
Mobile Information Systems
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Multilevel cell (MLC) phase change memory (PCM) shows great potential in terms of capacity and cost compared with single-level cell (SLC) PCM by storing multiple bits in one physical PCM cell. ...
Conventional PCM write schemes do not care for the modified-byte distribution among PCM chips and it just waits for the completion of the chip with the most amount of data. ...
For illustrative purpose, we assume the cache line is 512 bits with 256 physical cells. e conventional bit-mapping scheme is shown in Figure 8 . ...
doi:10.1155/2022/9552517
fatcat:43y6eagbcrbandqegwr6ngpnvq
LLS: Cooperative integration of wear-leveling and salvaging for PCM main memory
2011
2011 IEEE/IFIP 41st International Conference on Dependable Systems & Networks (DSN)
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Recent studies have revealed that a PCM chip which integrates millions to billions of bit cells has non-negligible variations in write endurance. ...
Wear leveling techniques have been proposed to balance write operations to different PCM regions. ...
Process Variation For PCM chips with billions of cells, some cells tend to fail earlier than others. ...
doi:10.1109/dsn.2011.5958221
dblp:conf/dsn/JiangDZCY11
fatcat:yq5ic3y7bbeubm57kifw7nvz3e
FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory
2012
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
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Multilevel Cell PCM (MLC) has the benefit of increased memory capacity with low fabrication cost. ...
In this paper, we propose Fine-grained write Power Budgeting (FPB) for MLC PCM. ...
Acknowledgments We thank the anonymous reviewers for their constructive suggestions, and Prof. Moinuddin K. Qureshi for sheparding the paper. ...
doi:10.1109/micro.2012.10
dblp:conf/micro/JiangZC012
fatcat:flp2d77pzrcmdctiuogk6gxhza
Design Methodologies for Reliable and Energy-efficient PCM Systems
[article]
2020
arXiv
pre-print
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First, writing to PCM cells incurs significantly higher latency and energy penalties than reading its content. Second, high operating voltages of PCM impacts its reliable operations. ...
In this work, we propose methodologies to tackle the bottlenecks, improving performance, reliability, energy consumption, and sustainability for a PCM system. ...
Each peripheral circuit consists of a sense amplifier (to read PCM cells) and a write driver (to program PCM cells). ...
arXiv:2011.13959v1
fatcat:sjwdb2ejtjduxn54be6fdojll4
Exploit imbalanced cell writes to mitigate write disturbance in dense phase change memory
2015
Proceedings of the 52nd Annual Design Automation Conference on - DAC '15
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., resetting a cell may disturb the values of its adjacent cells if these cells are in amorphous state. A preventive approach to mitigate WD errors is to allocate sufficient inter-cell thermal band. ...
In this paper, we propose to exploit the cell level write imbalance to mitigate WD errors. A memory line is often split into cell groups so that the cells within one group are written synchronously. ...
The logically unused bits, e.g., bit 900, may be mapped to cell 30 using D-XOR [7] . For a RESET to cell 31, its WD effect on cell 30 can be ignored as the logical bit in cell 30 is useless. ...
doi:10.1145/2744769.2744841
dblp:conf/dac/WangJZWY15a
fatcat:6vchshjhj5g45kmlpkh3k7v47i
Reliability-Performance Trade-offs in Neuromorphic Computing
[article]
2020
arXiv
pre-print
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We observe that the parasitic voltage drops create a significant asymmetry in programming speed and reliability of NVM cells in a crossbar. ...
Specifically, NVM cells that are on shorter current paths are faster to program but have lower endurance than those on longer current paths, and vice versa. ...
For such computing architectures, the weight of a synaptic connection is programmed as conductance of a PCM cell by driving current and inducing Joule heating in the cell. ...
arXiv:2009.12672v1
fatcat:5nr6vhxghjbrfi4a6auym4snpu
ELight: Enabling Efficient Photonic In-Memory Neurocomputing with Life Enhancement
[article]
2021
arXiv
pre-print
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The resultant large number of PCM writes leads to serious dynamic power and overwhelms the fragile PCM with limited write endurance. ...
In this work, we propose a synergistic optimization framework, ELight, to minimize the overall write efforts for efficient and reliable optical in-memory neurocomputing. ...
ACKNOWLEDGEMENT The authors acknowledge the Multidisciplinary University Research Initiative (MURI) program through the Air Force Office of Scientific Research (AFOSR), contract No. ...
arXiv:2112.08512v1
fatcat:5z2rbf4edbafnbslhtspbrbt3m
Enhancing the security of memory in cloud infrastructure through in‐phase change memory data randomisation
2021
IET Computers & Digital Techniques
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, which is an overhead-free method by reusing the cell programming mechanism in iterate-write PCM devices. ...
By observing the influence of process variation (PV) on PCM cell programming, they propose a fast and efficient in-memory data obfuscation mechanism to defend against memory attacks or information leakage ...
ACKNOWLEDGEMENT Xianzhong Zhou is grateful for financial support from NSFC (Grant No. 61704032) and Open Fund of State Key Laboratory of Computer Architecture (Grant No. CARCH201814). ...
doi:10.1049/cdt2.12023
fatcat:otiqeltiobap7ag6t454sqdzne
Secure and Durable (SEDURA)
2015
SIGPLAN notices
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introducing more writes to PCM cells. ...
Phase changing memory (PCM) is considered a promising candidate for next-generation main-memory. ...
These extra writes are crucial for PCM-based main memory since a PCM cell can only be programmed for 10 7 to 10 9 times [5] . ...
doi:10.1145/2808704.2754969
fatcat:vsrwl4lfb5g23kwnpc2nhkf6fe
A survey of power management techniques for phase change memory
2016
International Journal of Computer Aided Engineering and Technology
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The aim of this paper is to provide insights to researchers into working of PCM power-management techniques and also motivate them to propose even better techniques for designing future 'green' PCM-based ...
In this paper, we survey several techniques for managing power consumption of PCM. We also classify these techniques based on their characteristics to highlight their similarities and differences. ...
For states mapped at lower resistance values, they use single reset pulse programming and for states mapped at higher resistance values, they use staircase programming. ...
doi:10.1504/ijcaet.2016.10000092
fatcat:gnowq3m4jvfuhbqx2jhc27y27m
A Variable Length Coding Framework for Cost Function Reduction in Non-Volatile Memory Systems
[article]
2017
arXiv
pre-print
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Variable length coding for Non-Volatile Memory (NVM) technologies is a promising method to improve memory capacity and system performance through compressing memory blocks. ...
more than leading compression approaches and by 12.5% more than the flip-and-write approach which selects between the data and its complement based on the programming cost. ...
In addition to the asymmetry in energy and programming time, writing a bit value of 0 on PCM cells decreases the cell endurance more than writing a bit value of 1 [6] . ...
arXiv:1710.08940v1
fatcat:c7meneis4nh2vnxudmgie7gn6i
Improving write operations in MLC phase change memory
2012
IEEE International Symposium on High-Performance Comp Architecture
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In particular, multi-level cell (MLC) PCM that stores multiple bits in a single cell, offers high density with low per-byte fabrication cost. ...
Phase change memory (PCM) recently has emerged as a promising technology to meet the fast growing demand for large capacity memory in modern computer systems. ...
Acknowledgments We thank the anonymous referees for their valuable comments and suggestions. We also acknowledge the support from PCM@Pitt research group. ...
doi:10.1109/hpca.2012.6169027
dblp:conf/hpca/JiangZZYC12
fatcat:gxuqvu4mmjaizbhsbwvw25fwuu
Efficient scrub mechanisms for error-prone emerging memories
2012
IEEE International Symposium on High-Performance Comp Architecture
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In particular, multi-level cell (MLC) PCM devices will suffer from resistance drift, that increases the soft error rate and incurs high overheads for the scrub mechanism. ...
The scrub mechanism scans the memory looking for a single-bit error and corrects it before the line experiences a second uncorrectable error. ...
We assume the use of a Gray code mapping policy that ensures that adjacent states differ in only one bit. Thus, every drift-based cell error corresponds to only a single bit error. ...
doi:10.1109/hpca.2012.6168941
dblp:conf/hpca/AwasthiSSRBS12
fatcat:lxk2zvgl3jb7fhewedwhpa4ixq
AnalogNets: ML-HW Co-Design of Noise-robust TinyML Models and Always-On Analog Compute-in-Memory Accelerator
[article]
2021
arXiv
pre-print
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We evaluate the AnalogNets on a calibrated simulator, as well as real hardware, and find that accuracy degradation is limited to 0.8%/1.2% after 24 hours of PCM drift (8-bit) for KWS/VWW. ...
AnalogNets running on the 14nm AON-CiM accelerator demonstrate 8.58/4.37 TOPS/W for KWS/VWW workloads using 8-bit activations, respectively, and increasing to 57.39/25.69 TOPS/W with 4-bit activations. ...
NVM Cell Noise and Drift Resistive PCM cells are each programmed to a value within the minimum and maximum conductance limits (Figure 2 ). ...
arXiv:2111.06503v1
fatcat:tcrphrxtxredzmhwfxyjfnn5ku
SAWL:A Self-adaptive Wear-leveling NVM Scheme for High Performance Storage Systems
[article]
2019
arXiv
pre-print
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The idea behind SAWL is to dynamically tune the wear-leveling granularities and balance the writes across the cells of entire memory, thus achieving suitable tradeoff between the lifetime and cache hit ...
Moreover, to reduce the size of the address-mapping table, SAWL maintains a few recently-accessed mappings in a small on-chip cache. ...
For example, the SLC PCM devices are expected to last for 10 7 ∼ 10 8 writes per cell [9, 44] , and the RRAM technology has a per-cell write limit between 10 8 and 10 12 in the SLC mode. ...
arXiv:1905.02871v1
fatcat:gl2sjlcw65aybdo6iuvcedkete
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