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Billion-transistor architectures: there and back again

D. Burger, J.R Goodman
2004 Computer  
The second set described a number of visions for designs that could and would scale up to billion-transistor architectures (BTAs).  ...  Seven years later, it is both interesting and instructive to look back on that debate and the projections made. What did the community get right? What did we miss? What new ideas have since emerged?  ...  Similarly, scaling a single core to billions of transistors will also be highly inefficient, given the ILP limits in single threads.  ... 
doi:10.1109/mc.2004.1273999 fatcat:g3pgpbucqfbnbjdjdvxrygjtui

The limits of semiconductor technology and oncoming challenges in computer micro architectures and architectures

Mile Stojcev, Teufik Tokic, Ivan Milentijevic
2004 Facta universitatis - series Electronics and Energetics  
The technology that enabled this exponential growth is a combination of advancements in process technology, microarchitecture, architecture and design and development tools.  ...  In the last three decades the world of computers and especially that of microprocessors has been advanced at exponential rates in both productivity and performance.  ...  Exploitation of a billion transistor capacity of a single VLSI IC requires new system paradigms and significant improvements to design productivity.  ... 
doi:10.2298/fuee0403285s fatcat:gaxelp2aebbnvinhxssaydxhvy

■ SOFTWARE ARCHITECTURES [chapter]

2016 Computer Systems Architecture  
This book contains information obtained from authentic and highly regarded sources.  ...  Reasonable efforts have been made to publish reliable data and information, but the author and publisher cannot assume responsibility for the validity of all materials or the consequences of their use.  ...  According to a very conservative estimate, there are many billions of appliances capable of running Java.  ... 
doi:10.1201/9781315373287-17 fatcat:xdwgw43lt5h3ri3mgmq5u7olcu

Architecture, constraints, and behavior

J. C. Doyle, M. Csete
2011 Proceedings of the National Academy of Sciences of the United States of America  
Familiar and accessible case studies are used to illustrate concepts of robustness, organization, and architecture (modularity and protocols) that are central to understanding complex networks.  ...  from systems engineering, systems biology, and mathematics.  ...  There are ten times as many fibers feeding back from the primary visual cortex to the visual thalamus as there are in the forward "flow" (6) .  ... 
doi:10.1073/pnas.1103557108 pmid:21788505 pmcid:PMC3176601 fatcat:d3yqzs3oxrbl5e635kvsgcd74a

Effect of increasing chip density on the evolution of computer architectures

R. Nair
2002 IBM Journal of Research and Development  
Effect of increasing chip density on the evolution of computer architectures Trends in lithography and process technology indicate that billion-transistor computer chips will be possible well before the  ...  Nair has worked in the areas of computer architecture, design automation, and testing, and has several publications, patents, and IBM awards in these areas.  ...  Acknowledgment The author wishes to thank Jim Smith, Monty Denneau, Eric Kronstadt, and Dan Prener for many useful discussions and for valuable feedback on earlier versions of this manuscript.  ... 
doi:10.1147/rd.462.0223 fatcat:th2tvpf7ajfrxmfgs4mjznkud4

Idempotent processor architecture

Marc de Kruijf, Karthikeyan Sankaralingam
2011 Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture - MICRO-44 '11  
and hardware complexity.  ...  This paper presents a new processor architecture, the idempotent processor architecture, that advances both of these directions by presenting a new execution paradigm that allows speculative execution  ...  Again, region R6 executes with a mis-speculation occurring after some time. However, the idempotent processor recovers by simply jumping back to the beginning of the region.  ... 
doi:10.1145/2155620.2155637 dblp:conf/micro/KruijfS11 fatcat:cktbx6nww5gavorpghak76g72e

ARCHITECTURE AND IMPLEMENTATION ISSUES OF MULTI-CORE PROCESSORS AND CACHING – A SURVEY

Bhaskar Das .
2013 International Journal of Research in Engineering and Technology  
This paper includes what brought about the change from single processor architecture to having multiple processors on a single die and some of the hurdles involved, and the technologies behind it.  ...  Processor cache is the performance bottleneck in most current architectures.  ...  This transistor, nano-scale electronic switch, can switch between 1 and 0 states billions of times in a second. So, power is very much needed.  ... 
doi:10.15623/ijret.2013.0214016 fatcat:6h3jdy47mrbnhl7ckue2lyrnna

Drowsy caches

Krisztián Flautner, Nam Sung Kim, Steve Martin, David Blaauw, Trevor Mudge
2002 SIGARCH Computer Architecture News  
We show that with simple architectural techniques, about 80%-90% of the cache lines can be maintained in a drowsy state without affecting performance by more than 1%.  ...  We also argue that the use of drowsy caches can simplify the design and control of lowleakage caches, and avoid the need to completely turn off selected cache lines and lose their state.  ...  again.  ... 
doi:10.1145/545214.545232 fatcat:v2q33ll66jdhtioovbdvjjhkj4

A survey of checker architectures

Rajshekar Kalayappan, Smruti R. Sarangi
2013 ACM Computing Surveys  
We present a survey of different kinds of fault detection mechanisms for processors at the circuit, architecture, and software level.  ...  Reliability is quickly becoming a primary design constraint for high end processors because of the inherent limits of manufacturability, extreme miniaturization of transistors, and the growing complexity  ...  Traditional methods of design and testing are proving insufficient to ensure reliable error free operation for today's multi-billion transistor chips [Borkar 2004 ].  ... 
doi:10.1145/2501654.2501662 fatcat:rmmc2ntqofgkvnbjhwpmekol4i

Fundamental Underpinnings of Reconfigurable Computing Architectures

Andre DeHon
2015 Proceedings of the IEEE  
In this paper, we identify the major parameters that distinguish architectures in this design space and draw connections between these parameters and physical requirements (e.g., energy, delay, and area  ...  Reconfigurable architectures are a distinct point in the larger design space that includes programmable processors and nonprogrammable fixed-function devices.  ...  Vijayvargiya, and the anonymous IEEE reviewers for providing feedback on early drafts of this paper.  ... 
doi:10.1109/jproc.2014.2387696 fatcat:6ugselfn7fdudmar2k54ap7am4

Routing architecture exploration for regular fabrics

V. Kheterpal, A. J. Strojwas, L. Pileggi
2004 Proceedings of the 41st annual conference on Design automation - DAC '04  
We further propose new regular routing architectures and explore the various performance vs. manufacturability trade-offs.  ...  For example, there has been speculation [6] that regular logic fabrics [1] based on regular geometry patterns [2] can offer tighter control of variations and greater control of systematic manufacturing  ...  The configured metal architectures are incorporated back into "Dolphin" to facilitate netlist checking and post-routing timing reports.  ... 
doi:10.1145/996566.996625 dblp:conf/dac/KheterpalSP04 fatcat:4xyvvygb7jbivkha4wrb7fnmhq

Smart cache: A self adaptive cache architecture for energy efficiency

Karthik T. Sundararajan, Timothy M. Jones, Nigel Topham
2011 2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation  
In this paper we present a Set and way Management cache Architecture for Run-Time reconfiguration (Smart cache), a cache architecture that allows reconfiguration in both its size and associativity.  ...  Results show the energy-delay of the Smart cache is on average 14% better than state-of-the-art cache reconfiguration architectures.  ...  Shrinking feature sizes and increasing numbers of transistors packed into a single die only exacerbates this issue.  ... 
doi:10.1109/samos.2011.6045443 dblp:conf/samos/SundararajanJT11 fatcat:bfbtyz745bdgrnjc4nyortn63a

Cortical architectures on a GPGPU

Andrew Nere, Mikko Lipasti
2010 Proceedings of the 3rd Workshop on General-Purpose Computation on Graphics Processing Units - GPGPU '10  
We propose using a software work-queue structure to solve the former, and pipelining the cortical architecture during training phase for the latter.  ...  The GPGPU is a readily-available architecture that fits well with the parallel cortical architecture inspired by the basic building blocks of the human brain.  ...  As future technologies continue to scale down to ultra-small CMOS transistors, nano-tubes, or even individual molecules, we realize the number of devices available for future architectures will grow and  ... 
doi:10.1145/1735688.1735693 dblp:conf/asplos/NereL10 fatcat:rsyqfc54rngphhmz2v7ng7j6iq

Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip

Varadan Savulimedu Veeravalli, Thomas Polzer, Andreas Steininger, Ulrich Schmid
2012 2012 15th Euromicro Conference on Digital System Design  
This paper presents the architecture and a detailed design analysis of a digital measurement chip which facilitates long-term irradiation experiments of basic asynchronous circuits.  ...  A measurement architecture based on multiple non-rad-hard counters is used, which we show to be resilient against double faults, as well as many triple and even higher-multiplicity faults.  ...  Again this is easy to detect. Overall, this confirms that a single bit flip in the LFSR counter is witnessed as billions of skipped transitions.  ... 
doi:10.1109/dsd.2012.26 dblp:conf/dsd/VeeravalliPSS12 fatcat:dm3tzwk7ynee7oemw2nv6ktx7y

Architectural support for low overhead detection of memory violations

S. Ghose, L. Gilgeous, P. Dudnik, A. Aggarwal, C. Waxman
2009 2009 Design, Automation & Test in Europe Conference & Exhibition  
This paper proposes architectural support to detect memory reference violations in inherently unsafe languages such as C and C++.  ...  Violations in memory references cause tremendous loss of productivity, catastrophic mission failures, loss of privacy and security, and much more.  ...  SafeProc, on the other hand, uses a small fraction of the processor transistors (our studies show less than 0.1% for a billion transistor processor) to perform the operations required for memory violations  ... 
doi:10.1109/date.2009.5090747 dblp:conf/date/GhoseGDAW09 fatcat:i4acv5uqjrhjpfyj3gnjrnhmca
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